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ADSP-1981BL датащи(PDF) 19 Page - Analog Devices |
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ADSP-1981BL датащи(HTML) 19 Page - Analog Devices |
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19 / 32 page ![]() AD1981BL Rev. A | Page 19 of 32 RECORD SELECT CONTROL REGISTER Index 0x1A Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x1A Record Select X X X X X LS2 LS1 LS0 X X X X X RS2 RS1 RS0 0x0000 Used to select the record source independently for right and left. The default value is 0x0000, which corresponds to MIC In. Refer to Table 24 for examples. All registers are not shown, and bits containing an X are assumed to be reserved. Table 23. Bit Function RS [2:0] Right Record Select LS [2:0] Left Record Select Table 24. Settings for Record Select Control LS [10:8] Left Record Source RS [2:0] Right Record Source 000 MIC 000 MIC 001 CD_L 001 CD_R 010 Muted 010 Muted 011 AUX_L 011 AUX_R 100 LINE_IN_L 100 LINE_IN_R 101 Stereo Mix (L) 101 Stereo Mix (R) 110 Mono Mix 110 Mono Mix 111 PHONE_IN 111 PHONE_IN RECORD GAIN REGISTER Index 0x1C Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x1C Record Gain IM X X X LIM3 LIM2 LIM1 LIM0 RM1 X X X RIM3 RIM2 RIM1 RIM0 0x8000 1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 24 for examples. Table 25. Bit Mnemonic Function RIM [3:0] Right Input Mixer Gain Control Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB. RM Right-Channel Mute Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the IM bit. Otherwise, this bit always reads 0 and has no affect when set to 1. LIM [3:0] Left Input Mixer Gain Control Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB. IM Input Mute When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 0x76 is set to 1, in which case this mute bit affects only the left channel. |
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