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ADN2813 датащи(PDF) 13 Page - Analog Devices

номер детали ADN2813
подробное описание детали  Continuous Rate 10 Mb/s to 1.25 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
PDF  28 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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ADN2813 датащи(HTML) 13 Page - Analog Devices

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ADN2813
Rev. 0 | Page 13 of 28
JITTER SPECIFICATIONS
The ADN2813 CDR is designed to achieve the best bit-
error-rate (BER) performance and to exceed the jitter
transfer, generation, and tolerance specifications proposed
for SONET/SDH equipment defined in the Telcordia
Technologies specification.
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions, measured in unit intervals
(UI), where 1 UI = 1 bit period. Jitter on the input data can
cause dynamic phase errors on the recovered clock sampling
edge. Jitter on the recovered clock causes jitter on the
retimed data.
The following sections briefly summarize the specifications of
jitter generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level and the ADN2813
performance with respect to those specifications.
Jitter Generation
The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input. For SONET devices, the jitter generated
must be less than 0.01 UI rms and must be less than 0.1 UI p-p.
Jitter Transfer
The jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal vs. the frequency.
This parameter measures the limited amount of the jitter on an
input signal that can be transferred to the output signal (see
Figure 15).
0.1
ACCEPTABLE
RANGE
fC
JITTER FREQUENCY (kHz)
SLOPE = –20dB/DECADE
Figure 15. Jitter Transfer Curve
Jitter Tolerance
The jitter tolerance is defined as the peak-to-peak amplitude of
the sinusoidal jitter applied on the input signal, which causes a
1 dB power penalty. This is a stress test intended to ensure that
no additional penalty is incurred under the operating conditions
(see Figure 16).
15.00
1.50
0.15
f0
f1
f2
f3
f4
JITTER FREQUENCY (kHz)
SLOPE = –20dB/DECADE
Figure 16. SONET Jitter Tolerance Mask



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