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CYT2CL датащи(PDF) 76 Page - Infineon Technologies AG

номер детали CYT2CL
подробное описание детали  TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M4F single
PDF  174 Pages
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производитель  INFINEON [Infineon Technologies AG]
домашняя страница  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

CYT2CL датащи(HTML) 76 Page - Infineon Technologies AG

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Datasheet
76
002-32508 Rev. *F
2022-10-20
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral protection unit fixed structure pairs
129
DW0_CH_STRUCT56_CH
0x40288E00
0x00000040
P-DMA#0 Channel #56
130
DW0_CH_STRUCT57_CH
0x40288E40
0x00000040
P-DMA#0 Channel #57
131
DW0_CH_STRUCT58_CH
0x40288E80
0x00000040
P-DMA#0 Channel #58
132
DW0_CH_STRUCT59_CH
0x40288EC0
0x00000040
P-DMA#0 Channel #59
133
DW0_CH_STRUCT60_CH
0x40288F00
0x00000040
P-DMA#0 Channel #60
134
DW0_CH_STRUCT61_CH
0x40288F40
0x00000040
P-DMA#0 Channel #61
135
DW0_CH_STRUCT62_CH
0x40288F80
0x00000040
P-DMA#0 Channel #62
136
DW0_CH_STRUCT63_CH
0x40288FC0
0x00000040
P-DMA#0 Channel #63
137
DW0_CH_STRUCT64_CH
0x40289000
0x00000040
P-DMA#0 Channel #64
138
DW0_CH_STRUCT65_CH
0x40289040
0x00000040
P-DMA#0 Channel #65
139
DW0_CH_STRUCT66_CH
0x40289080
0x00000040
P-DMA#0 Channel #66
140
DW0_CH_STRUCT67_CH
0x402890C0
0x00000040
P-DMA#0 Channel #67
141
DW0_CH_STRUCT68_CH
0x40289100
0x00000040
P-DMA#0 Channel #68
142
DW0_CH_STRUCT69_CH
0x40289140
0x00000040
P-DMA#0 Channel #69
143
DW0_CH_STRUCT70_CH
0x40289180
0x00000040
P-DMA#0 Channel #70
144
DW0_CH_STRUCT71_CH
0x402891C0
0x00000040
P-DMA#0 Channel #71
145
DW0_CH_STRUCT72_CH
0x40289200
0x00000040
P-DMA#0 Channel #72
146
DW0_CH_STRUCT73_CH
0x40289240
0x00000040
P-DMA#0 Channel #73
147
DW0_CH_STRUCT74_CH
0x40289280
0x00000040
P-DMA#0 Channel #74
148
DW0_CH_STRUCT75_CH
0x402892C0
0x00000040
P-DMA#0 Channel #75
149
DW1_CH_STRUCT0_CH
0x40298000
0x00000040
P-DMA#1 Channel #0
150
DW1_CH_STRUCT1_CH
0x40298040
0x00000040
P-DMA#1 Channel #1
151
DW1_CH_STRUCT2_CH
0x40298080
0x00000040
P-DMA#1 Channel #2
152
DW1_CH_STRUCT3_CH
0x402980C0
0x00000040
P-DMA#1 Channel #3
153
DW1_CH_STRUCT4_CH
0x40298100
0x00000040
P-DMA#1 Channel #4
154
DW1_CH_STRUCT5_CH
0x40298140
0x00000040
P-DMA#1 Channel #5
155
DW1_CH_STRUCT6_CH
0x40298180
0x00000040
P-DMA#1 Channel #6
156
DW1_CH_STRUCT7_CH
0x402981C0
0x00000040
P-DMA#1 Channel #7
157
DW1_CH_STRUCT8_CH
0x40298200
0x00000040
P-DMA#1 Channel #8
158
DW1_CH_STRUCT9_CH
0x40298240
0x00000040
P-DMA#1 Channel #9
159
DW1_CH_STRUCT10_CH
0x40298280
0x00000040
P-DMA#1 Channel #10
160
DW1_CH_STRUCT11_CH
0x402982C0
0x00000040
P-DMA#1 Channel #11
161
DW1_CH_STRUCT12_CH
0x40298300
0x00000040
P-DMA#1 Channel #12
162
DW1_CH_STRUCT13_CH
0x40298340
0x00000040
P-DMA#1 Channel #13
163
DW1_CH_STRUCT14_CH
0x40298380
0x00000040
P-DMA#1 Channel #14
164
DW1_CH_STRUCT15_CH
0x402983C0
0x00000040
P-DMA#1 Channel #15
165
DW1_CH_STRUCT16_CH
0x40298400
0x00000040
P-DMA#1 Channel #16
166
DW1_CH_STRUCT17_CH
0x40298440
0x00000040
P-DMA#1 Channel #17
167
DW1_CH_STRUCT18_CH
0x40298480
0x00000040
P-DMA#1 Channel #18
168
DW1_CH_STRUCT19_CH
0x402984C0
0x00000040
P-DMA#1 Channel #19
169
DW1_CH_STRUCT20_CH
0x40298500
0x00000040
P-DMA#1 Channel #20
170
DW1_CH_STRUCT21_CH
0x40298540
0x00000040
P-DMA#1 Channel #21
171
DW1_CH_STRUCT22_CH
0x40298580
0x00000040
P-DMA#1 Channel #22
172
DW1_CH_STRUCT23_CH
0x402985C0
0x00000040
P-DMA#1 Channel #23
173
DW1_CH_STRUCT24_CH
0x40298600
0x00000040
P-DMA#1 Channel #24
Table 23-1
PPU fixed structure pairs (continued)
Pair No.
PPU fixed structure pair
Address
Size
Description



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