CS5161GD16 datasheet(12/18 Pages) ONSEMI

12 / 18 page

CS5161, CS5161H

http://onsemi.com

Figure 15. CS5161/5161H OVP Response to an

Input−to−Output Short Circuit by Pulling the Input

Voltage to Ground

M 5.00 ms

Trace 1− Regulator Output Voltage (1.0 V/div.)

Trace 4− 5.0 V from PC Power Supply (5.0 V/div.)

External Output Enable Circuit

On/off control of the regulator can be implemented

through the addition of two additional discrete components

(see Figure 16). This circuit operates by pulling the Soft

Start pin high, and the VFFB pin low, emulating a short

circuit condition.

Figure 16. Implementing Shutdown

with the CS5161/5161H

Shutdown

Input

5.0 V

MMUN2111T1 (SOT−23)

8 V

FFB

IN4148

CS5161

External Power Good Circuit

An optional Power Good signal can be generated through

the use of four additional external components (see Figure

17). The threshold voltage of the Power Good signal can be

adjusted per the following equation:

VPower Good +

(R1 ) R2)

0.65 V

This circuit provides an open collector output that drives

the Power Good output to ground for regulator voltages less

than VPower Good.

Figure 17. Implementing Power Good

with the CS5161/5161H

5.0 V

Power Good

10 k

VOUT

PN3904

6.2 k

PN3904

10 k

CS5161

Figure 18. CS5161/5161H During Power Up. Power

Good Signal is Activated when Output Voltage

Reaches 1.70 V.

M 2.50 ms

Trace 4− 5.0 V Input (2.0 V/div.)

Trace 3 − 12 V Input (VCC1) and (VCC2) (10 V/div.)

Trace 1− Regulator Output Voltage (1.0 V/div.)

Trace 2− Power Good Signal (2.0 V/div.)

Slope Compensation

The V2 control method uses a ramp signal, generated by

the ESR of the output capacitors, that is proportional to the

ripple current through the inductor. To maintain regulation,

the V2 control loop monitors this ramp signal, through the

PWM comparator, and terminates the switch on−time.

The stringent load transient requirements of modern

microprocessors require the output capacitors to have very

low ESR. The resulting shallow slope presented to the PWM

comparator, due to the very low ESR, can lead to pulse width

jitter and variation caused by both random or synchronous

noise.

Adding slope compensation to the control loop, avoids

erratic operation of the PWM circuit, particularly at lower

duty cycles and higher frequencies, where there is not

enough ramp signal, and provides a more stable switchpoint.

The scheme that prevents that switching noise

prematurely triggers the PWM circuit consists of adding a

positive voltage slope to the output of the Error Amplifier

(COMP pin) during an off−time cycle.

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