CS5159

http://onsemi.com

6

Figure 2. Block Diagram

−

+

−

+

−

+

SS

Comparator

Fast Feedback

LGnd

Slow Feedback

PWM

Comparator

SS Low

Comparator

SS High

Comparator

5 BIT

DAC

Comparator

Error

Amplifier

PGnd

FAULT

FAULT

FAULT

Latch

PGnd

R

S

Q

Q

R

S

Q

Q

R

S

Q

Latch

PMW

One Shot

Off−Time

Timeout

Time−Out

Timer

Edge Triggered

Extended

Off−Time

Timeout

Normal

Off−Time

Timeout

Maximum

On−Time

Timeout

(30 μs)

GATE(H) = ON

GATE(H) = OFF

2.0 μA

60 μA

5.0 V

0.7 V

2.5 V

1.0 V

−

+

−

+

+

−

3.90 V

3.85V

COMP

PWM COMP

APPLICATIONS INFORMATION

THEORY OF OPERATION

generated by the ESR of the output capacitors. This ramp is

proportional to the AC current through the main inductor

and is offset by the value of the DC output voltage. This

control scheme inherently compensates for variation in

either line or load conditions, since the ramp signal is

generated from the output voltage itself. This control

scheme differs from traditional techniques such as voltage

mode, which generates an artificial ramp, and current mode,

which generates a ramp from inductor current.

COMP

Reference

Voltage

+

+

PWM

Comparator

Ramp

Signal

Error

Amplifier

Error

Signal

Output

Voltage

Feedback

E

C

−

−