ADE7169ASTF16 datasheet(127/140 Pages) AD

127 / 140 page

Preliminary Technical Data

ADE7169F16

Rev. PrD | Page 127 of 140

Step 1: Write to SPITx SFR

Step 2: SS is asserted low and write routine is initiated

Step 3: Wait for SPITxIRQ Interrupt flag to write to SPITx SFR. Transfer will continue

until the SPITX register and transmit shift registers are empty.

Step 4: SPITxIRQ Interrupt Flag is set when SFRTx register is empty

Step 5: SS is deasserted high

Continuous

Step 6: Write to SPITx SFR to clear SPITxIRQ Interrupt flag

Figure 82

shows the SPI output for certain automatic chip select

and continuous mode selections. Note that if the continuous

mode is not used, a short delay is inserted between transfers.

SCLK

DOUT

DIN

DIN1

DIN2

AUTO_SS=1

SPICONT=0

SCLK

DOUT

DIN

DIN1

AUTO_SS=1

SPICONT=1

DIN2

AUTO_SS=0

SPICONT=0

(manual SS control)

DOUT1

DOUT2

DOUT1

DOUT2

SCLK

DOUT

DIN

DIN1

DIN2

DOUT1

DOUTz2

Figure 82: Automatic Chip Select and Continuous Mode Output

SPI INTERRUPT AND STATUS FLAGS

The SPI interface has several status flags that indicate the status

of the double buffered receive and transmit registers. Figure 83

shows when the status and interrupt flags are raised. The

transmit interrupt occurs when the transmit shift register is

loaded with the data in the SPI/I2C Transmit Buffer SFR

(SPI2CTx, 0x9A) register. If the SPI master is in transmit

operating mode and the SPI/I2C Transmit Buffer SFR

(SPI2CTx, 0x9A) register has not been written with new data by

the beginning of the next byte transfer, the transmit operation

stops.

When a new byte of data is received in the SPI Receive Buffer

SFR (SPI2CRx, 0x9B) register, the SPI receive interrupt flag is

raised. If the data in the SPI Receive Buffer SFR (SPI2CRx,

0x9B) register is not read before new data is ready to be loaded

into the SPI Receive Buffer SFR (SPI2CRx, 0x9B), an overflow

condition has occurred. This overflow condition, indicated by

the SPIRxOF flag, will force the new data to be discarded or

overwritten if the RxOF_EN bit is set.

SPITX

TRANSMIT SHIFT REGISTER

SPITxIRQ=1

SPITX (empty)

TRANSMIT SHIFT REGISTER

Stops Transfer if TIMODE=1

SPIRX

RECEIVE SHIFT REGISTER

SPIRxIRQ=1

SPIRX (full)

RECEIVE SHIFT REGISTER

SPIRxOF=1

Figure 83: SPI Receive and Transmit Interrupt and Status Flags

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