WMS7204

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TABLE 3 – A1 AND A0 ADDRESS BIT DECODE TABLE

[A1 A0]

[0 0]

[0 1]

[1 0]

[1 1]

Channel

0

1

2

3

A3 and A2 are the address bits that decide which NVMEM memory to be accessed, as shown in the

table below.

TABLE 4 – A3 AND A2 ADDRESS BIT DECODE TABLE

[A3 A2]

[0 0]

[0 1]

[1 0]

[1 1]

NVMEM

0

1

2

3

D7-D0 are the data values to be loaded into the Tap Register to set the wiper position, while D8 is

used to set the output mode. D8 has to be loaded into the NVMEM0~3 first and then the “Load Tap

Register” command (#6) has be executed to load D8 into the output-selection MUX to set the output

mode. D8=0 sets the output to Buffer Off mode while D8=1 sets to Buffer On mode.

FIGURE 5 – SPI COMMAND WAVEFORMS

CS

CS is taken LOW

before command

starts

CS is taken HIGH

after command is

sent

R/B

Note:

• A multiple of 24 bits must always be sent or the

command will not be valid

• Bits marked ‘x’ are don’t care bits.

R/B goes LOW at completion of commands

2, 4, 5, 6 and 7 to allow NVMEM to program

HIGH after command is sent.

SDO SDI must be valid on the rising edge of the clock SDO is valid on the falling edge of the clock or

CS

C3

`

C2 C1 C0 A3 A2 A1 A0 x

x x x

x x

x D8 D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 9 1

0

1

1

1

2

1

3

1

4

1

5

1

6

1

7

1

8

1

9

2

0

2

1

2

2

2

3

2

4

CLK

SD

I