SC18IS600_601_3

© NXP B.V. 2006. All rights reserved.

Product data sheet

Rev. 03 — 13 December 2006

11 of 28

NXP Semiconductors

SC18IS600/601

6.3 External clock input (SC18IS601)

In this device, the processor clock is derived from an external source driving the CLKIN

pin. The clock rate may be from 0 Hz up to 18 MHz.

to the bus, and it has the following features:

data on the bus

one serial bus

resume serial transfer

(Refer to Philips Semiconductors

9398 393 40011.)

6.5 Serial Peripheral Interface (SPI)

The host communicates with the SC18IS600/601 via the SPI interface. The

SC18IS600/601 operates in Slave mode up to 3 Mbit/s.

The SPI interface has four pins: SCLK, MOSI, MISO, and CS.

Data flows from the master to the SC18IS600/601 on the MOSI (Master Out Slave In)

pin and flows from SC18IS600/601 to the master on the MISO (Master In Slave Out)

pin. The SCLK signal is an input to the SC18IS600/601.

device as the current slave. An SPI slave device uses its CS pin to determine whether

it is selected. The CS pin may be tied LOW if it is the only device on the bus.

Typical connections are shown in Figure 11.

RPU

002aab716

SC18IS600/601

DEVICE

DEVICE

SDA

SCL

RPU