NP89N04PDK

Preliminary

R07DS1016EJ0200 Rev.2.00

Page 2 of 6

May 24, 2018

Electrical Characteristics (TA = 25°C)

Item

Symbol

MIN.

TYP.

MAX.

Unit

Test Conditions

Zero Gate Voltage Drain Current

IDSS

—

—

1

A

VDS = 40 V, VGS = 0 V

Gate Leakage Current

IGSS

—

—

100

nA

VGS =

20 V, VDS = 0 V

Gate to Source Threshold Voltage

VGS(th)

1.5

1.8

2.5

V

VDS = VGS, ID = 250

A

Forward Transfer Admittance *1

| yfs |

44

88

—

S

VDS = 5 V, ID = 45 A

Drain to Source On-state Resistance *1

RDS(on)1

—

2.45

2.95

m



VGS = 10 V, ID = 45 A

RDS(on)2

—

3.10

6.20

m



VGS = 4.5 V, ID = 23 A

Input Capacitance *2

Ciss

—

3900

5850

pF

VDS = 25 V

VGS = 0 V

f = 1 MHz

Output Capacitance *2

Coss

—

530

800

pF

Reverse Transfer Capacitance *2

Crss

—

200

360

pF

Turn-on Delay Time *2

td(on)

—

18

40

ns

VDD = 20 V, ID = 45 A

VGS = 10 V

RG = 0



Rise Time *2

tr

—

8

21

ns

Turn-off Delay Time *2

td(off)

—

71

142

ns

Fall Time *2

tf

—

9

23

ns

Total Gate Charge *2

QG

—

68

102

nC

VDD = 32 V

VGS = 10 V

ID = 90 A

Gate to Source Charge

QGS

—

17

—

nC

Gate to Drain Charge

QGD

—

11

—

nC

Body Diode Forward Voltage *1

VF(S-D)

—

0.9

1.5

V

IF = 90 A, VGS = 0 V

Reverse Recovery Time

trr

—

43

—

ns

IF = 90 A, VGS = 0 V

di/dt = 100 A/

s

Reverse Recovery Charge

Qrr

—

59

—

nC

Note: *1 Pulsed test

Note: *2 Not subject of production test. Verified by design/characterization.

TEST CIRCUIT 3 GATE CHARGE

VGS = 20 → 0 V

PG.

RG = 25 Ω

50

Ω

D.U.T.

L

VDD

TEST CIRCUIT 1 AVALANCHE CAPABILITY

PG.

D.U.T.

RL

VDD

TEST CIRCUIT 2 SWITCHING TIME

RG

PG.

IG = 2 mA

50

Ω

D.U.T.

RL

VDD

ID

VDD

IAS

VDS

BVDSS

Starting Tch

VGS

0

Duty Cycle

≤ 1%

τ = 1 μs

τ

VGS

Wave Form

VDS

Wave Form

VGS

VDS

10%

0

0

90%

90%

90%

VGS

V

DS

ton

toff

td(on)

tr

td(off)

tf

10%

10%