Nexperia

LSF0102

2-bit bidirectional multi-voltage level translator; open-drain; push-pull

12.1. Waveforms and test circuit

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output Bn, An

input An, Bn

tPHL

tPLH

VM

VM

VIH

VIL

VOH

VOL

VM

VM

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 6. The data input (An, Bn) to output (Bn, An) propagation delay times

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tf

10 %

10 %

90 %

90 %

90 %

10 %

10 %

VIH

0 V

VIH

negative

pulse

positive

pulse

0 V

90 %

tr

tr

tf

VI source waveform

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EN

up/down translating

refB

Bn

LSF0102

refA

An

Rpu

Vpu

VrefA

CEN

CL

S1

S2

VI

VO

VEXT

switch

S1

S2

Translating up

Translating down

RL

1 MΩ

Test circuit

Test data is given in Table 9.

The An and Bn pins may be exchanged.

All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; ZO = 50 Ω.

Definitions test circuit:

CL = Load capacitance including jig and probe capacitance; CEN = Decoupling capacitance;

Rpu = Pull-up resistance; RL = Load resistance; S1/S2 = Test selection switch

Fig. 7. Test circuit for measuring switching times

LSF0102

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© Nexperia B.V. 2020. All rights reserved

Product data sheet

Rev. 3 — 4 September 2020

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