LOW SKEW, ÷1/÷2,

3.3V LVPECL/ECL CLOCK GENERATOR

87322BI DATA SHEET

2

REVISION C 11/16/15

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

1V

CC

Power

Core supply pin.

2

MR

Input

Pulldown

Active High Master Reset. When logic HIGH, the internal dividers are reset

causing the true outputs (Qx) to go low and the inverted outputs (nQx) to go

high. When logic LOW, the internal dividers and the outputs are enabled.

LVCMOS / LVTTL interface levels.

3

DIV_SELA

Input

Pulldown

Selects divide value for Bank A output as described in Table 3C. LVCMOS /

LVTTL interface levels.

4

DIV_SELB

Input

Pulldown

Selects divide value for Bank B output as described in Table 3C. LVCMOS /

LVTTL interface levels.

5

CLK0

Input

Pulldown Non-inverting differential LVPECL clock input. LVPECL interface levels.

6

nCLK0

Input

Pullup

Inverting differential LVPECL clock input. LVPECL interface levels.

7

CLK_SEL

Input

Pulldown

Clock select. When HIGH, selects CLK1, nCLK1 inputs. When LOW, selects

CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels.

8

CLK1

Input

Pulldown Non-inverting differential LVPECL clock input. LVPECL interface levels.

9

nCLK1

Input

Pullup

Inverting differential LVPECL clock input. LVPECL interface levels.

10, 28, 29

nc

Unused

No connect.

11

DIV_SELC

Input

Pulldown

Selects divide value for Bank C output as described in Table 3C. LVCMOS /

LVTTL interface levels.

12

DIV_SELD

Input

Pulldown

Selects divide value for Bank D output as described in Table 3C. LVCMOS /

LVTTL interface levels.

13

V

EE

Power

Negative supply pin.

14, 27, 30, 39,

40, 47, 52

V

CCO

Power

Output supply pins.

15,16

nQD5, QD5

Output

Differential output pair. LVPECL interface levels.

17, 18

nQD4, QD4

Output

Differential output pair. LVPECL interface levels.

19, 20

nQD3, QD3

Output

Differential output pair. LVPECL interface levels.

21, 22

nQD2, QD2

Output

Differential output pair. LVPECL interface levels.

23, 24

nQD1, QD1

Output

Differential output pair. LVPECL interface levels.

25, 26

nQD0, QD0

Output

Differential output pair. LVPECL interface levels.

31, 32

nQC3, QC3

Output

Differential output pair. LVPECL interface levels.

33, 34

nQC2, QC2

Output

Differential output pair. LVPECL interface levels.

35, 36

nQC1, QC1

Output

Differential output pair. LVPECL interface levels.

37, 38

nQC0, QC0

Output

Differential output pair. LVPECL interface levels.

41, 42

nQB2, QB2

Output

Differential output pair. LVPECL interface levels.

43, 44

nQB1, QB1

Output

Differential output pair. LVPECL interface levels.

45, 46

nQB0, QB0

Output

Differential output pair. LVPECL interface levels.

48, 49

nQA1, QA1

Output

Differential output pair. LVPECL interface levels.

50, 51

nQA0, QA0

Output

Differential output pair. LVPECL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.