Preliminary Datasheet

VSC7216-01

Multi-Gigabit Interconnect Chip

VITESSE

SEMICONDUCTOR CORPORATION

G52352-0, Rev 3.2

Page 3

05/05/01

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The REFCLK signal can be either single-ended TTL or differential LVPECL. If TTL, connect the TTL

input to REFCLKP but leave REFCLKN open. If LVPECL, connect the inputs to REFCLKP and REFCLKN.

Serial and parallel data rates for all channels may be halved by means of the RATE pin. When RATE is

HIGH, the chip is in full-speed mode (default mode of operation) and when LOW, the half-speed mode is

selected. Table 1 shows the interaction of the DUAL and RATE inputs.

Table 1: Using the RATE input to Achieve Half-Speed Operation

Transmitter Functional Description

Transmitter Data Bus

Each VSC7216-01 transmit channel has an 8-bit input transmit data character, Tn(7:0), and two control

inputs, C/Dn and WSENn. The C/Dn input determines whether a normal data character or a special “K-

character” is transmitted, and the WSENn input initiates transmission of a 16-character “Word Sync Sequence”

used to align the receive channels. These data and control inputs are clocked either on the rising edge of

REFCLK, on the rising edge of TBCn, or within the data eye formed by TBCn. When not using REFCLK, each

channel uses either its own TBCn input, or uses the TBCA input. The transmit interface mode is controlled by

TMODE(2:0) as shown in Table 2.

Table 2: Transmit Interface Input Timing Mode

RATE Pin

DUAL Pin

Clock

Multiplication

Factor

Serial Link

Speed

Parallel

Data Rate

REFCLK

Frequency

0

0

x10

500Mb/s

50Mb/s

50MHz

0

1

x20

500Mb/s

50Mb/s

25MHz

1

0

x10

1Gb/s

100Mb/s

100MHz

1

1

x20

1Gb/s

100Mb/s

50MHz

TMODE(2:0)

Input Timing Reference

0 0 0

REFCLK Rising Edge

0 0 1

0 1 0

0 1 1

Reserved

1 0 0

TBCA Rising Edge

1 0 1

TBCn Rising Edge

1 1 0

TBCA Data Eye

1 1 1

TBCn Data Eye