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January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

Instruction Register (IR)

The Instruction register allows an instruction to be shifted serially into the CPS-10Q at the rising edge of TCK. The instruction is then used to select the

test to be performed or the test register to be accessed, or both. The instruction shifted into the register is latched at the completion of the shifting

process, when the TAP controller is at the Update-IR state.

The Instruction Register contains four shift-register-based cells that can hold instruction data. This register is decoded to perform the following func-

tions:

– To select test data registers that may operate while the instruction is current. The other test data registers should not interfere with chip oper-

ation and selected data registers.

– To define the serial test data register path used to shift data between TDI and TDO during data register scanning.

The Instruction Register is comprised of 4 bits to decode instructions, as shown in the table below.

Instruction

Definition

OPcode

[3:0]

EXTEST

Mandatory instruction allowing the testing of board level interconnections.

Data is typically loaded onto the latched parallel outputs of the boundary scan

shift register using the SAMPLE/PRELOAD instruction prior to use of the

EXTEST instruction. EXTEST will then hold these values on the outputs while

being executed. Also see the CLAMP instruction for similar capability.

0000

SAMPLE/

PRELOAD

Mandatory instruction that allows data values to be loaded onto the latched

parallel output of the boundary-scan shift register prior to selection of the other

boundary-scan test instruction. The Sample instruction allows a snapshot of

data flowing from the system pins to the on-chip logic or vice versa.

0001

IDCODE

Provided to select Device Identification to read out manufacturer’s identity,

part, and version number.

0010

HIGHZ

Tri-states all output and bidirectional boundary scan cells.

0011

CLAMP

Provides JTAG user the option to bypass the part’s JTAG controller while

keeping the part outputs controlled similar to EXTEST.

0100

EXTEST_PULSE AC Extest instruction implemented in accordance with the requirements of the

IEEE std. 1149.6 specification.

0101

EXTEST_TRAIN AC Extest instruction implemented in accordance with the requirements of the

IEEE std. 1149.6 specification.

0110

RESERVED

Behaviorally equivalent to the BYPASS instruction as per the IEEE std. 1149.1

specification. However, the user is advised to use the explicit BYPASS instruc-

tion.

0111 — 1001

CONFIGURA-

TION REGIS-

TER ACCESS

(CRA)

CPS-10Q-specific opcode to allow reading and writing of the configuration reg-

isters. Reads and writes must be 32-bits. See further detail below.

1010

PRIVATE

For internal use only. Do not use.

1011 — 1100

RESERVED

Behaviorally equivalent to the BYPASS instruction as per the IEEE std. 1149.1

specification. However, the user is advised to use the explicit BYPASS instruc-

tion.

1101

PRIVATE

For internal use only. Do not use.

1110

BYPASS

The BYPASS instruction is used to truncate the boundary scan register as a

single bit in length.

1111

Table 30 Instructions Supported by CPS-10Q JTAG Boundary Scan