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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ICS954101 датащи(PDF) 14 Page - Renesas Technology Corp |
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ICS954101 датащи(HTML) 14 Page - Renesas Technology Corp |
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14 / 18 page  14 Integrated Circuit Systems, Inc. ICS954101 0815G—12/02/08 Test Clarification Table Comments FS_C/TEST_ SEL HW PIN FS_B/TEST_ MODE HW PIN TEST ENTRY BIT B6b6 REF/N or HI-Z B6b7 OUTPUT 0X0X NORMAL 10 X 0 HI-Z 10 X 1 REF/N 11 X 0 REF/N 11 X 1 REF/N 0X1 0 HI-Z 0X1 1 REF/N B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B6b7: 1= REF/N, Default = 0 (HI-Z) HW SW · FS_C/TEST_SEL is a 3-level latched input. o Power-up w/ V >= 2.0V to select TEST o Power-up w/ V < 2.0V to have pin function as FS_C. · When pin is FS_C, VIH_FS and VIL_FS levels apply. · FS_B/TEST_MODE is a low-threshold input o VIH_FS and VIL_FS levels apply. o TEST_MODE is a real time input · TEST_SEL can be invoked after power up through SMBus B6b6. o If TEST is selected by B6b6, only B6b7 controls TEST_MODE. The FS_B/TEST_Mode pin is not used. · Power must be cycled to exit TEST. |
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