Byte 1: Active/Inactive Register

(1= enable, 0 = disable)

BIT

PIN# PWD

DESCRIPTION

Bit7

-

X

FS3#

Bit6

10

1

AGP1

Bit5

9

1

AGP0

Bit4

28

1

48MHz

Bit3

2

1

IOAPIC

Bit2

55

1

CPUCLK_F

Bit1

54

1

CPUCLK0

Bit0

53

1

CPUCLK1

Byte 3: Active/Inactive Register

(1= enable, 0 = disable)

BIT

PIN#

PWD

DESCRIPTION

Bit7

-

X

FS0#

Bit6

-

X

FS1#

Bit5

-

X

FS2#

Bit4

12

1

PCICLK_F

Bit3

-

1

Reserved

Bit2

39,38

1

SDRAMT3,SDRAMC3

Bit1

35,34

1

SDRAMT4,SDRAMC4

Bit0

33,32

1

SDRAMT5,SDRAMC5

Byte 5: Active/Inactive Register

(1= enable, 0 = disable)

BIT

PIN# PWD

DESCRIPTION

Bit7

-

1

Reserved

Bit6

-

1

Reserved

Bit5

-

1

Reserved

Bit4

-

1

Reserved

Bit3

-

1

Reserved

Bit2

-

1

Reserved

Bit1

-

1

Reserved

Bit0

-

1

Reserved

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

2. Latched Frequency Selects (FS#) will be inverted logic

load of the input frequency select pin conditions.

0664---07/29/02

5

ICS951702

Advance Information

Byte 2: Active/Inactive Register

(1= enable, 0 = disable)

BIT

PIN# PWD

DESCRIPTION

Bit7

13

1

PCICLK0

Bit6

14

1

PCICLK1

Bit5

15

1

PCICLK2

Bit4

18

1

PCICLK3

Bit3

19

1

PCICLK4

Bit2

51,50

1

SDRAMT0,SDRAMC0

Bit1

47,46

1

SDRAMT1,SDRAMC1

Bit0

45,44

1

SDRAMT2,SDRAMC2

Byte 4: Active/Inactive Register

(1= enable, 0 = disable)

BIT

PIN# PWD

DESCRIPTIO N

Bit 7

-

1

Reserved

Bit 6

20

1

PCICLKS

Bit 5

23

1

PCICLK6

Bit4

23

1

PCICLK6;1=1X,0=2X

Bit 3

-

1

Reserved

Bit 2

-

1

Reserved

Bit 1

-

1

Reserved

Bit0

33,

1

SDRAMT6,SDRAMC6

32

Byte 6: Active/Inactive Register

(1= enable, 0 = disable)

BIT

PIN# PWD

DESCRIPTION

Bit7

-

0

Reserved

Bit6

-

0

Reserved

Bit5

-

0

Reserved

Bit4

-

0

Reserved

Bit3

-

0

Reserved

Bit2

-

1

Reserved

Bit1

-

1

Reserved

Bit0

-

1

Reserved

Note: Don't write into this register, writing into this

register can cause malfunction