IDTTM/ICSTM

Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems

1211B—09/17/09

ICS951464

IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8

TM - based Systems

3

Pin Description (Continued)

PIN #

PIN NAME

TYPE

DESCRIPTION

29

*CLKREQC#

IN

Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled.

0 = enabled, 1 = tri-stated

30

ATIGCLKC1

OUT

Complementary clock of differential ATIGCLK clock pair.

31

ATIGCLKT1

OUT

True clock of differential ATIGCLK clock pair.

32

GNDATIG

PWR

Ground for ATIG clocks

33

VDDATIG

PWR

Power supply ATIG clocks, nominal 3.3V

34

ATIGCLKC0

OUT

Complementary clock of differential ATIGCLK clock pair.

35

ATIGCLKT0

OUT

True clock of differential ATIGCLK clock pair.

36

VDDSRC

PWR

Supply for SRC clocks, 3.3V nominal

37

GNDSRC

PWR

Ground pin for the SRC outputs

38

SRCCLKC0

OUT

Complement clock of differential SRC clock pair.

39

SRCCLKT0

OUT

True clock of differential SRC clock pair.

40

IREF

OUT

This pin establishes the reference current for the differential current-mode output pairs. This

pin requires a fixed precision resistor tied to ground in order to establish the appropriate

current. 475 ohms is the standard value.

41

GNDA

PWR

Ground pin for the PLL core.

42

VDDA

PWR

3.3V power for the PLL core.

43

CPUCLK8C1

OUT

Complementary clock of differential 3.3V push-pull K8 pair.

44

CPUCLK8T1

OUT

True clock of differential 3.3V push-pull K8 pair.

45

GNDCPU

PWR

Ground pin for the CPU outputs

46

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

47

CPUCLK8C0

OUT

Complementary clock of differential 3.3V push-pull K8 pair.

48

CPUCLK8T0

OUT

True clock of differential 3.3V push-pull K8 pair.

49

*CLKREQA#

IN

Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled.

0 = enabled, 1 = tri-stated

50

GNDHTT

PWR

Ground pin for the HTT outputs

51

HTTCLK0

OUT

3.3V Hyper Transport output

52

VDDHTT

PWR

Supply for HTT clocks, nominal 3.3V.

53

**PD

IN

Asynchronous active high input pin used to power down the device. The internal clocks are

disabled and the VCO is stopped.

54

FS2/REF2

I/O

Frequency select latch input pin / 14.318 MHz reference clock.

55

FS1/REF1

I/O

Frequency select latch input pin / 14.318 MHz reference clock.

56

FS0/REF0

I/O

Frequency select latch input pin / 14.318 MHz reference clock.