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ICS950818 датащи(PDF) 5 Page - Renesas Technology Corp

номер детали ICS950818
подробное описание детали  Frequency Generator with 200MHz Differential CPU Clocks
PDF  20 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS950818 датащи(HTML) 5 Page - Renesas Technology Corp

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ICS950818
BYTE
Affected Pin
Control Function
Type
Bit Control
0
Pin #
Name
0
1
PWD
Bit7
-
Spread Enabled
Spread Spectrum Control
RW
OFF
ON
0
Power down mode output level
Bit 6
-
CPUCLKT(1 :0)
0= CPU driven in power down
RW
x2 IREF
Hi-Z
0
1= undriven
Bit 5
31
3V66 1NCH CLK
VCH/66.66 Select
RW
66.66
48.00
0
Bit4
44
CPU STOP#
Reflects value of pin
R
Stop
Active
X
Bit3
30
PCI_STOP#
Reflects value of pin at power up.
RW
Stop
Active
X
Also can be set.
Bit2
-
-
(Reserved)
R
-
-
X
Bit 1
46
FS1
Freauencv Selection
R
-
-
X
Bit 0
36
FS0
Freauencv Selection
R
-
-
X
Note: For PCI_STOP# function, refer to table2.
BYTE
Affected Pin
Control Function
Type
Bit Control
1
Pin #
Name
0
1
PWD
Bit7
-
-
(Reserved)
R
-
-
X
CPU_Stop mode output level
Bit 6
-
CPUCLKT(1 :0)
0= CPU driven when stopped
RW x2 IREF Hi-Z
0
1 = undriven
Bit 5
39,38
CPUCLKT1 ,CPUCLKC1
Allow control of output with
RW
Not
Freerun
0
(see note)
assertion of CPU STOP#.
Freerun
Bit4
43,42
CPUCLKT0,CPUCLKC0
Allow control of output with
RW
Not
Freerun
0
(see note)
assertion of CPU STOP#.
Freerun
Bit3
-
-
(Reserved)
R
-
-
X
Bit2
39,38
CPUCLKT1 , CPUCLKC1
Output control
RW Disable Enable
1
Bit 1
43,42
CPUCLKT0, CPUCLKC0
Output control
RW Disable Enable
1
Bit 0
-
-
(Reserved)
R
-
-
X
Note: CPUCLK(1 :0) can be turned on/off by CPU_STOP#. Refer to table3.
BYTE
Affected Pin
Control Function
Type
Bit Control
2
Pin #
Name
0
1
PWD
Bit7
47
REF
1X or 0.5X Strength control
RW
1X
0.5X
0
Bit 6
14
PCICLK5
Output control
RW Disable Enable
1
Bit 5
13
PCICLK4
Output control
RW Disable Enable
1
Bit4
12
*PCICLK3
Output control
RW Disable Enable
1
Bit3
-
-
Reserved
X
-
-
1
Bit2
10
*PCICLK2
Output control
RW
Disable
Enable
1
Bit 1
9
PCICLK1
Output control
RW
Disable
Enable
1
Bit 0
8
PCICLK0
Output control
RW
Disable
Enable
1
Note: PCICLK(5 :0) can be turned on/off by PCI_STOP#. Refer to table2.
0825F-11/19/03
5



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