11

ICS94201

0428B - 11/28/05

Absolute Maximum Ratings

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress

specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections

of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product

reliability.

Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V

I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V

Ambient Operating Temperature . . . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C

Group Timing Relationship Table

1

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input High Voltage

VIH

2VDD+0.3

V

Input Low Voltage

VIL

VSS-0.3

0.8

V

Input High Current

IIH

VIN = VDD

-5

5

µA

IIL1

VIN = 0 V; Inputs with no pull-up resistors

-5

IIL2

VIN = 0 V; Inputs with pull-up resistors

-200

CL = max cap loads;

CPU=66-133 MHz, SDRAM=100 MHz

334

350

CPU=133 MHz, SDRAM=133 MHz

465

500

IDD2.5OP

CL = max cap loads;

20

70

Powerdown Current

IDD3.3PD

CL = 0 pF; Input address to VDD or GND

280

600

µA

Input Frequency

Fi

VDD = 3.3 V

14.318

MHz

Pin Inductance

Lpin

7nH

CIN

Logic Inputs

5

pF

COUT

Output pin capacitance

6

pF

CINX

X1 & X2 pins

27

45

pF

Transition time

1

Ttrans

To 1st crossing of target frequency

3

ms

Settling time

1

Ts

From 1st crossing to 1% target frequency

3

ms

Clk Stabilization

1

TSTAB

From VDD = 3.3 V to 1% target frequency

3

ms

tPZH,tPZL

Output enable delay (all outputs)

1

10

ns

tPHZ,tPLZ

Output disable delay (all outputs)

1

10

ns

1Guaranteed by design, not 100% tested in production.

Delay

1

Input Capacitance

1

Input Low Current

µA

IDD3.3OP

Operating Supply

Current

mA

Offset

Tolerance

Offset

Tolerance

Offset

Tolerance

Offset

Tolerance

CPU to SDRAM

2.5 ns

500 ps

5.0 ns

500 ps

0.0 ns

500 ps

3.75 ns

500 ps

CPU to 3V66

7.5 ns

500 ps

5.0 ns

500 ps

0.0 ns

500 ps

0.0 ns

500 ps

SDRAM to 3V66

0.0 ns

500 ps

0.0 ns

500 ps

0.0 ns

500 ps

3.75 ns

500 ps

3V66 to PCI

1.5-3.5ns

500 ps

1.5-3.5ns

500 ps

1.5-3.5ns

500 ps

1.5-3.5ns

500 ps

PCI to IOAPIC

0.0 ns

1.0 ns

0.0 ns

1.0 ns

0.0 ns

1.0 ns

0.0 ns

1.0 ns

USB & DOT

Asynch

N/A

Asynch

N/A

Asynch

N/A

Asynch

N/A

1Guaranteed by design, not 100% tested in production.

Group

SDRAM 100 MHz

SDRAM 100 MHz

SDRAM 100 MHz

SDRAM 133 MHz

CPU 66 MHz

CPU 100 MHz

CPU 133 MHz

CPU 133 MHz