4

ICS93732

0578J—06/20/08

Notes:

1.

Refers to transition on noninverting output.

2.

While the pulse skew is almost constant over frequency, the duty cycle error

increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, where

the cycle (tc) decreases as the frequency goes up.

Timing Requirements

TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Operating Clock Frequency

freqop

Input Voltage level: 0-2.50V

22

340

MHz

Input Clock Duty Cycle

1

dtin

40

50

60

%

Clock Stabilization

1

tSTAB

from VDD = 2.5V to 1% target frequency

100

µs

1. Guaranteed by design, not 100% tested in production.

Switching Characteristics

TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V ± 0.20V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

66 MHz

100

120

100 / 125/ 133/167MHz

48

65

200/267MHz

47

75

Phase Error

1

tpe

-150

150

ps

Output to output Skew

1

Tskew

20

100

ps

66 MHz to 100MHz

49.5

50

50.5

%

101MHz to 267 MHz

49

49.4

51

%

Rise Time, Fall Time

4

tR , tf

Load=120Ω/14pF

579

950

ps

ps

tc-c

Duty Cycle (Sign Ended)

1,3

DC

Cycle to cycle Jitter

1,2