ICS91305I

HIGH PERFORMANCE COMMUNICATION BUFFER

IDT® HIGH PERFORMANCE COMMUNICATION BUFFER

4

ICS91305I

REV G 090612

Switching Characteristics

Notes:

1. Guaranteed by design and characterization. Not subject to 100% test.

2. REF input has a threshold voltage of 1.4V

3. All parameters expected with loaded outputs

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

Output period

t1

With CL=30pF

100.00

(10)

7.5

(133)

ns

(MHz)

Input period

t1

With CL=30pF

100.00

(10)

7.5

(133)

ns

(MHz)

Duty Cycle1

Dt1

Measured at 1.4V; CL=30pF

40.0

50

60

%

Duty Cycle1

Dt2

Measured at VDD/2 Fout

<66.6MHz

45

50

55

%

Rise Time1

tr1

Measured between 0.8V and 2.0V:

CL=30pF

1.2

1.5

ns

Fall Time1

tf1

Measured between 2.0V and 0.8V;

CL=30pF

1.2

1.5

ns

Delay, REF Rising

Edge to CLKOUT

Rising Edge1, 2

Dr1

Measured at 1.4V

0

±350

ps

Output to Output

Skew1

Tskew

All outputs equally loaded,

CL=20pF

250

ps

Device to Device

Skew1

Tdsk-Tdsk

Measured at VDD/2 on the

CLKOUT pins of devices

0

700

ps

Cycle to Cycle

Jitter1

Tcyc-Tcyc

Measured at 66.66 MHz, loaded

outputs

200

ps

PLL Lock Time1

t

LOCK

Stable power supply, valid clock

presented on REF pin

1.0

ms

Jitter; Absolute

Jitter1

Tjabs

@ 10,000 cycles

C

L = 30pF

-200

70

200

ps

Jitter; 1 - Sigma1

Tj1s

@ 10,000 cycles

C

L = 30pF

14

60

ps