ICS870919BVI REVISION B JANUARY 10, 2012

10

©2012 Integrated Device Technology, Inc.

ICS870919I Data Sheet

LVCMOS CLOCK GENERATOR

Schematic Layout

Figure 1 shows an example of 870919I application schematic. In this

example, the device is operated at VDD = AVDD = 3.3V. As with any

high speed analog circuitry, the power supply pins are vulnerable to

random noise. To achieve optimum jitter performance, power supply

isolation is required. The 870919I provides separate power supplies

to isolate any high switching noise from coupling into the internal PLL.

In order to achieve the best possible filtering, it is recommended that

the placement of the filter components be on the device side of the

PCB as close to the power pins as possible. If space is limited, the

0.1µF capacitor in each power pin filter should be placed on the

device side. The other components can be on the opposite side of the

PCB.

Power supply filter recommendations are a general guideline to be

used for reducing external noise from coupling into the devices. The

filter performance is designed for a wide range of noise frequencies.

This low-pass filter starts to attenuate noise at approximately 10kHz.

If a specific frequency noise component is known, such as switching

power supplies frequencies, it is recommended that component

values be adjusted and if required, additional filtering be added.

Additionally, good general design practices for power plane voltage

stability suggests adding bulk capacitance in the local area of all

devices.

The schematic example focuses on functional connections and is not

configuration specific. Refer to the pin description and functional

tables in the datasheet to ensure that the logic control inputs are

properly set.

Figure 1. 870919I Application Schematic

R4

35

REF_SEL

R5

35

nQ5

VDD

VDD

RU2

Not Install

VDD

nPE

Set Logic

Input to

'1'

Receiver

VDD

muRata, BLM18BB221SN1

FB1

1

2

RD2

1K

3.3V

2XQ

RU1

1K

Zo = 50

F REQ_SEL

Logic Control Input Examples

Q0

LOCK

To Logic

Input

pins

C4

0.1uF

Unused output can be left floating. There

should no trace attached to unused output.

Device characterized with all outputs

terminated.

Q/2

Receiver

AVDD

C7

0.1uF

Ro ~ 7 O hm

Q1

Driver_LVCMOS

Zo = 50

FEEDBACK

C3

0.1uF

VDD

Q3

C6

0.1uF

QE/nRST

VDD

R1

1-2

Q1

R3

43

Set Logic

Input to

'0'

R6

0

VDD

VDD=3.3V

Zo = 50 Ohm

SYNC0

Q0

U1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

28

27

26

25

GND

nQ5

VDD

OE/nRST

FEEDBACK

REF_SEL

SYNC0

AVDD

nPE

AGND

SYNC1

FREQ_SEL

GND

Q0

VDD

Q1

GND

PLL_EN

LOCK

GND

Q2

VDD

Q3

GND

Q4

VDD

2XQ

Q/2

C1

10uF

2XQ

C8

10uF

RD1

Not Install

To Logic

Input

pins

R2

35

C5

0.1uF

C2

0.1uF

Q2

SYNC1

PLL_EN

VDD

VDD

VDD

AGND