ICS85214

LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

IDT™ / ICS™ HSTL FANOUT BUFFER

3

ICS85214AG

REV. B

JUNE 3, 2016

Function Tables

Table 3A. Control Input Function Table

After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.

In the active mode, the state of the outputs are a function of the CLK0, CLK0 inputs as described in Table 3B.

Figure 1. CLK_EN Timing Diagram

Table 3B. Clock Input Function Table

NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.

Inputs

Outputs

CLK_EN

Q0:Q4

Q0:Q4

0

Enabled

Enabled

1

Disabled; LOW

Disabled; HIGH

Inputs

Outputs

Input to Output Mode

Polarity

CLK0 or CLK1

CLK0

Q[0:4]

Q[0:4]

0

1

LOW

HIGH

Differential to Differential

Non-Inverting

1

0

HIGH

LOW

Differential to Differential

Non-Inverting

0

Biased; NOTE 1

LOW

HIGH

Single-Ended to Differential

Non-Inverting

1

Biased; NOTE 1

HIGH

LOW

Single-Ended to Differential

Non-Inverting

Biased; NOTE 1

0

HIGH

LOW

Single-Ended to Differential

Inverting

Biased; NOTE 1

1

LOW

HIGH

Single-Ended to Differential

Inverting

Enabled

Disabled

CLK0

CLK_EN

CLK0

Q0:Q4

Q0:Q4