ICS840271I

SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR

IDT™ / ICS™ SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR

2

ICS840271BGI REV. A APRIL 23, 2009

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Function Tables

Table 3. SEL[1:0] Function Table

NOTE: REF = Input clock signal frequency

Number

Name

Type

Description

1VDDA

Power

Analog supply pin.

2

SEL0

Input

Pulldown

Selects the input reference frequency and the PLL bypass mode.

LVCMOS/LVTTL interface levels. See Table 3.

3

CLK

Input

Pulldown

Non-inverting differential clock input.

4

nCLK

Input

Pullup/

Pulldown

Inverting differential clock input. Internal resistor bias to VDD/2.

5

SEL1

Input

Pullup

Selects the input reference frequency and the PLL bypass mode.

LVCMOS/LVTTL interface levels. See Table 3.

6

GND

Power

Power supply ground.

7

Q

Output

Single-ended clock output. LVCMOS/LVTTL interface levels.

8VDD

Power

Core supply pin.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

CIN

Input Capacitance

4

pF

RPULLUP

Input Pullup Resistor

51

k

Ω

RPULLDOWN Input Pulldown Resistor

51

k

Ω

ROUT

Output Impedance

VDD = 3.465V

16

Ω

VDD = 2.625V

19

Ω

Inputs

Mode

Output (MHz)

SEL1

SEL0

CLK, nCLK (MHz)

0

0

REF

PLL Bypass

REF/ 5

0

1

161.1328125

PLL Enabled

25

1 (default)

0 (default)

156.25

PLL Enabled

25

1

1

125

PLL Enabled

25