RT3602AE datasheet(40/46 Pages) RICHTEK

40 / 46 page

RT3602AE

www.richtek.com

DS3602AE-00 August 2017

is a registered trademark of Richtek Technology Corporation.

Over-Current Protection

The RT3602AE has dual OCP mechanism. One is named

SUM-OCP, the other is called SPIKE-OCP. The over current

protection (OCP) forces high-side MOSFET and low-side

MOSFET off by shutting down internal PWM logic drivers.

The RT3602AE provides SUM-OCP which is 160% of

IMON_04. IMON_04 is the current that makes (VIMON

−

VREF = 0.4V). When output current is higher than the SUM-

OCP threshold, SUM-OCP is latched with a 40

μs delay

time to prevent false trigger. Besides, the SUM-OCP

function is masked when dynamic VID transient occurs

and after dynamic VID transition, SUM-OCP is masked

for 80

μs. The other one is SPIKE-OCP which should trip

when the output current exceeds SPIKE_OCP threshold

during first DVID. SPIKE_OCP threshold is dependent

on IMAX level as shown in Table 4 and Table 5. When

output current is higher than the SPIKE-OCP threshold,

SPIKE-OCP is latched with a 1

μs delay time to prevent

false trigger.

Output Over-Voltage Protection

An OVP condition is detected when the VSEN pin is

350mV more than VID. When OVP is detected, the high-

side gate voltage UGATEx is pulled low and the low-side

gate voltage LGATEx is pulled high. OVP is latched with

a 0.5us delay- to prevent false trigger.

Negative Voltage Protection

Since the OVP latch continuously turns on all low-side

MOSFETs of the VR, the VR will suffer negative output

voltage. When the VSEN detects a voltage below

−0.07V

after triggering OVP, the VR triggers NVP to turn off all

low-side MOSFETs of the VR while the high-side

MOSFETs remain off. After triggering NVP, if the output

voltage rises above 0V, the OVP latch restarts to turn on

all low-side MOSFETs. Therefore, the output voltage may

bounce between 0V and

−0.07V due to OVP latch and

NVP triggering. The NVP function will be active only after

OVP is triggered.

Table 7. SET3 Pin Setting for DVIDTH





SET3_I

R1 x R2

V80μA

R1 R2

DVIDTH_ MAIN

(mV)

DVIDTH_ AUXI

(mV)

Min

Typ

Max

Unit

60.07331

75.07331

90.07331

160.1711

175.1711

190.1711

260.2688

275.2688

290.2688

360.3666

375.3666

390.3666

Disable

460.4643

475.4643

490.4643

560.5621

575.5621

590.5621

660.6598

675.6598

690.6598

760.7576

775.7576

790.7576

Disable

860.8553

875.8553

890.8553

960.9531

975.9531

990.9531

1061.051

1076.051

1091.051

1161.149

1176.149

1191.149

Disable

1261.246

1276.246

1291.246

Disable

1361.344

1376.344

1391.344

1461.442

1476.442

1491.442

1561.54

1576.54

1591.54

Disable

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