HT45R36 datasheet(13/40 Pages) HOLTEK

13 / 40 page

HT45R36

Rev. 1.00

September 28, 2006

tine execution will be delayed by one or more cycles. If

the wake-up results in the next instruction execution,

this will be executed immediately after the dummy pe-

riod is finished.

To minimise power consumption, all the I/O pins should

be carefully managed before entering the Power Down

mode.

Reset

There are three ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

A WDT time-out, when the device is in the Power Down

mode, is different from other device reset conditions, in

that it can perform a

²warm reset² that resets only the

Program Counter and the SP, leaving the other circuits

in their original state. Some registers remain unchanged

during other reset conditions. Most registers are reset to

their

²initial condition² when the reset conditions are

met. By examining the PDF and TO flags, the program

can distinguish between the different device reset types.

TO PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

WDT time-out during normal operation

WDT wake-up HALT

Note:

²u² means ²unchanged²

To guarantee that the system oscillator is started and

stabilised, the SST or System Start-up Timer, provides

an extra-delay of 1024 system clock pulses when the

system is reset (power-up, WDT time-out or RES reset)

or when the system awakens from a Power Down state.

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en-

able the SST delay.

An extra option load time delay is added during a system

reset (power-up, WDT time-out at normal mode or RES

reset).

The functional unit device reset status are shown below.

Program Counter

000H

Interrupt

Disable

Prescaler

Clear

WDT

Clear. After master reset,

WDT begins counting

Timer/Event Counter

Off

Input/Output Ports

Input mode

Stack Pointer

Points to the top of the stack

W a r m R e s e t

W D T

H A L T

C o l d

R e s e t

R E S

S y s t e m R e s e t

S S T

1 0 - b i t R i p p l e

C o u n t e r

O S C 1

Reset Configuration

R E S

V D D

1 0 0 k W

1 0 k W

0 . 1 m F *

0 . 0 1 m F *

Reset Circuit

Note:

²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

t S S T

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

Reset Timing Chart

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