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GLT6400L08LL-85ST датащи(PDF) 1 Page - List of Unclassifed Manufacturers |
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GLT6400L08LL-85ST датащи(HTML) 1 Page - List of Unclassifed Manufacturers |
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1 / 10 page ![]() G -LINK GLT6400L08 Ultra Low Power 512k x 8 CMOS SRAM Feb 2001(Rev. 1.1) G-Link Technology Corporation 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 1 - Features : Description : ∗ Low-power consumption. -active: 45mA at 85ns. -stand by : 20 µA (CMOS input / output) 5 µA (CMOS input / output, SL) ∗ Single +2.7 to 3.3V power supply. ∗ Equal access and cycle time. ∗ 85 ns access time at 2.7V to 3.3V 70ns access time at 3V to 3.6V ∗ 1.0V data retention mode. ∗ TTL compatible, tri-state input/output. ∗ Automatic power-down when deselected. ∗ Industrial grade (-40°C ~ 85°C) available. ∗ Package available: sTSOP , SOP. The GLT6400L08 is a low power CMOS Static RAM organized as 524,288 x 8 bits. Easy memory expansion is provided by an active LOW CE1 an active LOW OE , and Tri-state I/O’s. This device has an automatic power-down mode feature when deselected. Writing to the device is accomplished by taking chip Enable 1 ( CE1 ) with Write Enable ( WE ) LOW. Reading from the device is performed by taking Chip Enable 1 ( CE1 ) with Output Enable ( OE ) LOW while Write Enable ( WE ) and Chip Enable 2 (CE2) is HIGH. The I/O pins are placed in a high-impedance state when the device is deselected : the outputs are disabled during a write cycle. The GLT6400L08 comes with a 1V data retention feature and Lower Standby Power. The GLT6400L08 is available in a 32-pin sTSOP packages,and 32pin SOP package. Function Block Diagram : Cell Array INPUT BUFFER COLUMN DECODER CONTROL CIRCUIT OE WE CE1 CE2 I/O7 I/O1 Column Address |
Аналогичный номер детали - GLT6400L08LL-85ST |
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Аналогичное описание - GLT6400L08LL-85ST |
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