MPC5553 datasheet(20/60 Pages) FREESCALE

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MPC5553 Microcontroller Data Sheet, Rev. 0

Preliminary—Subject to Change Without Notice

Electrical Characteristics

Freescale Semiconductor

3.10

eQADC Electrical Characteristics

Frequency Modulation Range Limit 14

(fsysMax must not be exceeded)

Cmod

0.8

2.4

%fsys

ICO Frequency.

fico=[fref*(MFD+4)]/(PREDIV+1)

fico

fsys

MHz

Predivider Output Frequency (to PLL)

fPREDIV

4fMAX

MHz

1 All internal registers retain data at 0 Hz.

2 Up to the maximum frequency rating of the device (see Table 1).

3 “Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.

4 Self clocked mode (SCM) frequency is the frequency that the PLL operates at when the reference frequency falls below f

LOR.

This frequency is measured on the CLKOUT pin with the divider set to divide-by-2 of the system clock. NOTE: In SCM, the

MFD and PREDIV have no effect and the RFD is bypassed.

5 This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,

Vextal – Vxtal >= 400mV criteria has to be met for oscillator’s comparator to produce output clock.

6 This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,

Vxtal –Vextal >= 400mV criteria has to be met for oscillator’s comparator to produce output clock.

7 I

xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.

8 C

PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively

9 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the

synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time will also include the crystal

startup time.

10 PLL is operating in 1:1 PLL mode.

11 VDDE = 3.0 to 3.6V

12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

sys.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage

for a given interval. CLKOUT divider set to divide-by-2.

13 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of jitter + Cmod.

14 Modulation depth selected must not result in f

sys value greater than the fsys maximum specified value.

15 f

sys = fico / (2

RFD)

Table 13. eQADC Conversion Specifications (Operating)

Num

Characteristic

Symbol

Min

Max

Unit

ADC Clock (ADCLK) Frequency1

FADCLK

112

MHz

Conversion Cycles

Differential

Single Ended

13+2 (or 15)

14+2 (or 16)

13+128 (or 141)

14+128 (or 142)

ADCLK

cycles

Stop Mode Recovery Time2

TSR

—

µs

Resolution3

—1.25

—

INL: 6 MHz ADC Clock

INL6

–4

Counts3

INL: 12 MHz ADC Clock

INL12

–8

Counts

Table 12. HiP7 FMPLL Electrical Specifications (continued)

(VDDSYN = 3.0V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH)

Num

Characteristic

Symbol

Min.

Value

Max.

Value

Unit

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