HT36B4 datasheet(11/38 Pages) HOLTEK

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HT36B4

Rev. 1.00

October 18, 2006

Watchdog Timer

- WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator) or instruction clock (sys-

tem clock of the MCU divided by 4), determined by mask

options. This timer is designed to prevent a software

malfunction or sequence jumping to an unknown loca-

tion with unpredictable results. The Watchdog Timer can

be disabled by mask option. If the Watchdog Timer is

disabled, all the executions related to the WDT result in

no operation.

Once the internal WDT oscillator (RC oscillator with a

period of 78

ms normally) is selected, it is first divided by

256 (8-stages) to get the nominal time-out period of ap-

proximately 20ms. This time-out period may vary with

temperature, VDD and process variations. By invoking

the WDT prescaler, longer time-out periods can be real-

ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the

WDTS) can give different time-out periods. If WS2,

WS1, WS0 all equal to 1, the division ratio is up to 1:128,

and the maximum time-out period is 2.6 seconds.

If the WDT oscillator is disabled, the WDT clock may still

come from the instruction clock and operate in the same

manner except that in the HALT state the WDT may stop

counting and lose its protecting purpose. In this situation

the logic can only be restarted by external logic. The

high nibble and bit 3 of the WDTS are reserved for user

defined flags, and the programmer may use these flags

to indicate some specified status.

WS2

WS1

WS0

Division Ratio

000

1:1

001

1:2

010

1:4

011

1:8

1:16

1:32

1:64

1:128

If the device operates in a noisy environment, using the

on-chip RC oscillator (WDT OSC) is strongly recom-

mended, since the HALT will stop the system clock.

The WDT overflow under normal operation will initialize

²chip reset² and set the status bit TO. Whereas in the

HALT mode, the overflow will initialize a

²warm reset²

only the program counter and SP are reset to zero. To

clear the WDT contents (including the WDT prescaler ),

3 methods are implemented; external reset (a low level

to RES), software instructions, or a HALT instruction.

The software instructions include CLR WDT and the

other set

- CLR WDT1 and CLR WDT2. Of these two

types of instructions, only one can be active depending

on the mask option

-²CLR WDT times selection op-

tion

².Ifthe ²CLR WDT² is selected (i.e. CLRWDT times

equal one), any execution of the CLR WDT instruction

will clear the WDT. In case

²CLR WDT1² and ²CLR

WDT2

² are chosen (i.e. CLRWDT times equal two),

these two instructions must be executed to clear the

WDT; otherwise, the WDT may reset the chip because

of time-out.

Power Down Operation

- HALT

The HALT mode is initialized by a HALT instruction and

results in the following...

· The system oscillator will turn off but the WDT oscilla-

tor keeps running (If the WDT oscillator is selected).

Watchdog Timer

- WDT

· The contents of the on-chip RAM and registers remain

unchanged

· The WDT and WDT prescaler will be cleared and

starts to count again (if the clock comes from the WDT

oscillator).

· All I/O ports maintain their original status.

· The PDF flag is set and the TO flag is cleared.

· The HALT pin will output a high level signal to disable

the external ROM.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialization and the WDT overflow per-

forms a

²warm reset². By examining the TO and PDF

flags, the cause for a chip reset can be determined. The

PDF flag is cleared when there is a system power-up or by

executing the CLR WDT instruction and it is set when a

HALT instruction is executed. The TO flag is set if the WDT

time-out occurs, and causes a wake-up that only resets

the program counter and stack pointer, the others remain

in their original status.

f O S C / 8

8 - b i t C o u n t e r

W D T P r e s c a l e r

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

M a s k

O p t i o n

S e l e c t

W D T

O S C

Watchdog Timer

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