3

ICS9212- 13

0272F—08/08/07

Multo

Mult1

A

B

PLLCLK for REFCLK=50MHz

PLLCLK for REFCLK=66.66MHz

0041

Reserved

266.6

0161

300

400.0

1

0

16

3

266.7

355.5

1181

400

533.3

PLL Divider Selection and PLL Values (PLLCLK = REFCLK*A/B)

Power Management Modes

State

PwrDnB

StopB

NORMAL

1

1

Clk Off

1

0

Powerdown

0

X

Mode

FS0

FS1

FS2

Bypclk (int.)

BusClk

BusClkB

Normal

0

0

0

Gnd

PAclk

PAclkB

Bypass

1

0

0

PLLclk

PLLclk

PLLclkB

Test

1

1

0

Refclk

Refclk

RefclkB

Vendor Test A

0

0

1

-

-

-

Vendor Test B

1

0

1

-

-

-

Reserved

111

-

-

-

Output Test (OE)

0

1

X

-

Hi-Z

Hi-Z

Bypass and Test Mode Selection