ICS9173B

VIDEO GENLOCK PLL

CLOCK SYNTHESIZER

IDT® VIDEO GENLOCK PLL

3

ICS9173B

REV D 012913

Using the ICS9173B in Genlock Applications

Most video sources, such as video cameras, are

asynchronous, free-running devices. To digitize video or

synchronize one video source to another free-running

reference video source, a video “genlock” (generator lock)

circuit is required. The ICS9173B integrates the analog

blocks which make the task much easier.

In the complete video genlock circuit, the primary function of

the ICS9173B is to provide the analog circuitry required to

generate the video dot clock within a PLL. This application

is illustrated in Figure 1. The input reference signal for this

circuit is the horizontal synchronization (H-SYNC) signal. If

a composite video reference source is being used, the

h-sync pulses must be separated from the composite signal.

A video sync separator circuit, such as the National

Semiconductor LM1881, can be used for this purpose.

The clock feedback divider shown in Figure 1 is a digital

divider used within the PLL to multiply the reference

frequency. Its divide ratio establishes how many video dot

clock cycles occur per h-sync pulse. For example, if 880

pixel clocks are desired per h-sync pulse, then the divider

ratio is set to 880. Hence, together the h-sync frequency and

external divider ratio establish the dot clock frequency:

fOUT = fIN x N where N is external divide ratio

Both input pins IN and FBIN respond only to negative-going

clock edges of the input signal. The H-SYNC signal must be

constant frequency in the 12 kHz to 1 MHz range and stable

(low clock jitter) for creation of a stable output clock.

The output hook-ups of the ICS9173B are dictated by the

desired dot clock frequency. The primary consideration is

the internal VCO which operates over a frequency range of

10 MHz to 75 MHz. Because of the selectable VCO output

divider and the additional divider on output CLK2, four

distinct output frequency ranges can be achieved. The

following Table lists these ranges and the corresponding

device configuration.

Note that both outputs, CLK1 and CLK2, are available

during operation even though only one is fed back via the

external clock divider.

Pin 5, OE, tristates both CLK1 and CLK2 upon logic low

input. This feature can be used to revert dot clock control to

the system clock when not in genlock mode (hence, when in

genlock mode the system dot clock must be tristated).

When unused, inputs FS0 and OE must be tied to either

GND (logic low) or VDD (logic high).

Figure 1: Typical Application of ICS9173B in a Video Genlock System

FS0

State

Output

Used

Frequency/Range

ICS9173B-01

Frequency/Range

IcS9173B-15

0

CLK1

10 to 75 MHz

5 to 37.5 MHz

0

CLK2

5 to 37.5 MHz

2.5 to 18.75 MHz

1

CLK1

2.5 to 18.75 MHz

1.25 to 9.375 MHz

1

CLK2

1.25 to 9.375 MHz

0.625 to 4.6875 MHz