2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL/ECL CLOCK

MULTIPLEXER

7

Rev C 1/5/15

85356 DATA SHEET

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both VSWING and VOH must meet the

VPP and VCMR input requirements. Figures 2A to 2F show interface

examples for the CLK/nCLK input driven by the most common

driver types. The input interfaces suggested here are examples

only. Please consult with the vendor of the driver component to

confirm the driver termination requirements. For example, in Figure

2A, the input termination applies for IDT open emitter LVHSTL

drivers. If you are using an LVHSTL driver from another vendor,

use their termination recommendation.

Figure 2A. CLK/nCLK Input Driven by an

IDT Open Emitter LVHSTL Driver

Figure 2C. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 2E. CLK/nCLK Input Driven by a

3.3V HCSL Driver

Figure 2B. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 2D. CLK/nCLK Input Driven by a

3.3V LVDS Driver

Figure 2F. CLK/nCLK Input Driven by a

2.5V SSTL Driver

R1

50

Ω

R2

50

Ω

1.8V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVHSTL

IDT

LVHSTL Driver

Differential

Input

HCSL

*R3

*R4

CLK

nCLK

3.3V

3.3V

Differential

Input

CLK

nCLK

Differential

Input

SSTL

2.5V

Zo = 60

Ω

Zo = 60

Ω

2.5V

3.3V

R1

120

Ω

R2

120

Ω

R3

120

Ω

R4

120

Ω