ICS853S031I Data Sheet

LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

ICS853S031BYI REVISION A AUGUST 17, 2011

3

©2011 Integrated Device Technology, Inc.

Function Tables

Table 3A. Control Input Function Table

After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.

In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B.

Figure 1. CLK_EN Timing Diagram

Table 3B. Clock Input Function Table

Note 1: Please refer to the Applications Information, “Wiring the Differential Input to Accept Single Ended Levels”.

Inputs

Outputs

CLK_EN

CLK_SEL

Selected Sources

Q0:Q8

nQ0:nQ8

0

0

CLK, nCLK

Disabled:LOW

Disabled: HIGH

0

1

PCLK, nPCLK

Disabled:LOW

Disabled: HIGH

1

0

CLK, nCLK

Enabled

Enabled

1

1

PCLK, nPCLK

Enabled

Enabled

Inputs

Outputs

Input to Output Mode

Polarity

CLK or PCLK

nCLK or nPCLK

Q0:Q8

nQ0:nQ8

0

1

LOW

HIGH

Differential to Differential

Non-Inverting

1

0

HIGH

LOW

Differential to Differential

Non-Inverting

0

Biased; NOTE 1

LOW

HIGH

Single-Ended to Differential

Non-Inverting

1

Biased; NOTE 1

HIGH

LOW

Single-Ended to Differential

Non-Inverting

Biased; NOTE 1

0

HIGH

LOW

Single-Ended to Differential

Inverting

Biased; NOTE 1

1

LOW

HIGH

Single-Ended to Differential

Inverting

Enabled

Disabled

nCLK, nPCLK

CLK, PCLK

CLK_EN

nQ[0:8]

Q[0:8]