ICS8535-01 DATA SHEET

LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL

FANOUT BUFFER

10

REVISION F 08/11/14

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS8535-01.

Equations and example calculations are also provided.

1.

Power Dissipation.

The total power dissipation for the ICS8535-01 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•

Power (core)MAX =VCC_MAX *IEE_MAX = 3.465V * 50mA = 173.25mW

•

Power (outputs)MAX = 30mW/Loaded Output pair

If all outputs are loaded, the total power is 4 * 30mW = 120mW

Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 120mW = 293.25mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C.

The equation for Tj is as follows: Tj =



JA * Pd_total + TA

Tj = Junction Temperature



JA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance



JA must be used. Assuming a moderate air

flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6A below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.293W * 66.6°C/W = 89.5°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (single layer or multi-layer).

Table 6A. Thermal Resistance



JA for 20-Lead TSSOP, Forced Convection

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Table 6B.



JA vs. Air Flow Table for 20-Lead VFQFN



JA by Velocity

Linear Feet per Minute

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

114.5°C/W

98.0°C/W

88.0°C/W

Multi-Layer PCB, JEDEC Standard Test Boards

73.2°C/W

66.6°C/W

63.5°C/W



JA by Velocity

Meters per Second

013

Multi-Layer PCB, JEDEC Standard Test Boards

60.4°C/W

52.8°C/W

46.0°C/W