ICS8432-101 datasheet(2/21 Pages) RENESAS

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IDT™ / ICS™ 700MHZ, 3.3V LVPECL FREQUENCY SYNTHESIZER

ICS8432DY-101 REV. C APRIL 10, 2007

ICS8432-101

700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

event occurs. As a result, the M and N bits can be hardwired to

set the M divider and N output divider to a specific default state

that will automatically occur during power-up. The TEST output

is LOW when operating in the parallel input mode. The relation-

ship between the VCO frequency, the input frequency and the M

divider is defined as follows:

The M value and the required values of M0 through M8 are

shown in Table 3B, Programmable VCO Frequency Function

Table. Valid M values for which the PLL will achieve lock for a

25MHz reference are defined as 8

≤ M ≤ 28. The frequency out

is defined as follows:

Serial operation occurs when nP_LOAD is HIGH and S_LOAD is

LOW. The shift register is loaded by sampling the S_DATA

bits with the rising edge of S_CLOCK. The contents of the shift reg-

ister are loaded into the M divider and N output divider when S_LOAD

transitions from LOW-to-HIGH. The M divide and N output divide

values are latched on the HIGH-to-LOW transition of S_LOAD. If

S_LOAD is held HIGH, data at the S_DATA input is passed directly

to the M divider and N output divider on each rising edge of

S_CLOCK.

The

serial

mode

can

used

program the M and N bits and test bits T1 and T0. The internal

registers T0 and T1 determine the state of the TEST output as fol-

lows:

Time

SERIAL LOADING

PARALLEL LOADING

M, N

FUNCTIONAL DESCRIPTION

NOTE: The functional description that follows describes opera-

tion using a 25MHz clock input. Valid PLL loop divider values

for different input frequencies are defined in the Input Frequency

Characteristics, Table 5, NOTE 1.

The ICS8432-101 features a fully integrated PLL and there-

fore requires no external components for setting the loop band-

width. A differential clock input is used as the input to the

ICS8432-101. This input is fed into the phase detector. A 25MHz

clock input provides a 25MHz phase detector reference fre-

quency. The VCO of the PLL operates over a range of 250MHz

to 700MHz. The output of the M divider is also applied to the

phase detector.

The phase detector and the M divider force the VCO output

frequency to be M times the reference frequency by adjusting

the VCO control voltage. Note, that for some values of M (ei-

ther too high or too low), the PLL will not achieve lock. The

output of the VCO is scaled by a divider prior to being sent to

each of the LVPECL output buffers. The divider provides a 50%

output duty cycle.

The programmable features of the ICS8432-101 support two in-

put modes to program the PLL M divider and N output divider.

The two input operational modes are parallel and serial. Figure1

shows the timing diagram for each mode. In parallel mode, the

nP_LOAD input is initially LOW. The data on inputs M0 through

M8 and N0 and N1 is passed directly to the M divider and

N output divider. On the LOW-to-HIGH transition of the

nP_LOAD input, the data is latched and the M divider remains

loaded until the next LOW transition on nP_LOAD or until a serial

fVCO = f

x M

TEST Output

LOW

S_Data, Shift Register Input

Output of M divider

CMOS Fout

FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS

*NOTE: The NULL timing slot must be observed.

*NULL N1

M7M6

M5M4

M3M2

M1M0

S_CLOCK

S_DATA

S_LOAD

nP_LOAD

M0:M8, N0:N1

nP_LOAD

S_LOAD

fOUT = fVCO = f

x M

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