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ICS1893AFILF датащи(PDF) 115 Page - Renesas Technology Corp

номер детали ICS1893AFILF
подробное описание детали  3.3-V 10Base-T/100Base-TX Integrated PHYceiver
PDF  137 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS1893AFILF датащи(HTML) 115 Page - Renesas Technology Corp

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Chapter 10
DC and AC Operating Conditions
ICS1893AF, Rev. D 10/26/04
October, 2004
115
ICS1893AF Data Sheet - Release
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
10.5.2
Timing for Transmit Clock (TXCLK) Pins
Table 10-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various
interfaces. Figure 10-3 shows the timing diagram for the time periods.
Figure 10-3.
Transmit Clock Timing Diagram
Table 10-9.
Transmit Clock Timing
Time
Period
Parameter
Conditions
Min.
Typ.
Max. Units
t1
TXCLK Duty Cycle
–
35
50
65
%
t2a
TXCLK Period
100M MII (100Base-TX)
–
40
–
ns
t2b
TXCLK Period
10M MII (10Base-T)
–
400
–
ns
t1
t2x
TXCLK



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