ICS1893BF datasheet(38/133 Pages) RENESAS

38 / 133 page

ICS1893BF, Rev. F, 5/13/10

May, 2010

Chapter 6 Functional Blocks

ICS1893BF Data Sheet - Release

Upon receipt of an ESD, the Receive state machine returns to the IDLE state without passing the ESD to

the MAC Interface. Detection of an error forces the Receive state machine to assert the receive error signal

(RX_ER) and wait for the next symbol. If the ICS1893BF Receive state machine detects a premature end,

it forces the assertion of the RX_ER signal, sets the Premature End bit (bit 17.5) to logic one, and

transitions to the IDLE State.

6.3.4.2 PMA Receive Modules

The ICS1893BF has a PMA Receive module that provides the following functions:

• NRZI Decoding

The Receive module performs the NRZI decoding on the serial bit stream received from the Twisted-Pair

Physical Medium Dependent (TP-PMD) sublayer. It converts the bit stream to a unipolar, positive, binary

format that the PMA subsequently passes to the PCS.

• Receive Clock Recovery

The Receive Clock Recovery function consists of a phase-locked loop (PLL) that operates on the serial

data stream received from the PMD sublayer. This PLL automatically synchronizes itself to the clock

encoded in the serial data stream and then provides both a recovered clock and data stream to the PCS.

• Link Monitoring

– The ICS1893BF’s PMA Link Monitoring function observes the Receive Clock PLL. If the Receive

Clock PLL cannot acquire ‘lock’ on the serial data stream, it asserts an error signal. The status of this

error signal can be read in the QuickPoll Detailed Status Register’s PLL Lock Error bit (bit 17.9). This

bit is a latching high (LH) bit. (For more information on latching high and latching low bits, see Section

7.1.4.1, “Latching High Bits” and Section 7.1.4.2, “Latching Low Bits”.)

– In addition, the ICS1893BF’s PMA Link Monitor function continually audits the state of the connection

with the remote link partner. It asserts a receive channel error if a receive signal is not detected or if

a PLL Lock Error occurs. These errors, in turn, generate a link fault and force the link monitor

function to clear both the Status Register’s Link Status bit (bit 1.2) and the QuickPoll Detailed Status

6.3.5 PCS Control Signal Generation

For the PCS sublayer, there are two control signals: a Carrier Sense signal (CRS) and a Collision Detect

signal (COL).

The CRS control signals is generated as follows:

1. When a logic zero is detected in an idle bit stream, the Receive Functions examines the ensuing bits.

2. When the Receive Functions find the first two non-contiguous zero bits, the Receive state machine

moves into the Carrier Detect state.

3. As a result, the Boolean Receiving variable is set to TRUE.

4. Consequently, the Carrier Sense state machine moves into the Carrier Sense ‘on’ state, which asserts

the CRS signal.

5. If the PCS Functions:

a. Cannot confirm either the /I/J/ (IDLE, J) symbols or the /J/K/ symbols, the receive error signal

(RX_ER) is asserted, and the Receive state machine returns to the IDLE state. In IDLE, the

Boolean Receiving variable is set to FALSE, thereby causing the Carrier Sense state machine to

set the CRS signal to FALSE.

b. Can confirm the /I/J/K/ symbols, then the Receive state machine transitions to the ‘Receive’ state.

The COL control signal is generated by the transmit modules. For details, see Section 6.3.3.1, “PCS

Transmit Module”.

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