ICS1893 datasheet(111/153 Pages) RENESAS

111 / 153 page

Chapter 9

Pin Diagram, Listings, and Descriptions

ICS1893 Rev C 6/6/00

June, 2000

111

ICS1893 - Release

HW/SW

Input

Hardware/Software (Select).

When the signal on this pin is logic:

• Low, this pin selects Hardware mode operations.

• High, this pin selects Software mode operations.

LOCK

Output

(Stream Cipher) Lock (Acquired).

When the signal on this pin is logic:

• Low, the ICS1893 does not have a lock on the data stream.

• High, the ICS1893 has a lock on the data stream.

LSTA

Output

Link Status.

This pin is used to report the status of the link segment. When the

signal on this pin is logic:

• Low, there is no link established.

• High, there is a link established.

This pin is mapped according to the interface for which the ICS1893 is

mapped. For the:

• Media Independent Interface (MII), the LSTA is mapped as LSTA.

• 100M Symbol Interface, the LSTA is mapped as SD.

• 10M Serial Interface, the LSTA is mapped as LSTA.

• Link Pulse Interface, the LSTA is mapped as SD.

MII/SI

Input

Media Independent Interface / Stream Interface (Select).

This pin is used in combination with the 10/LP and 10/100SEL pins to

configure the ICS1893 MAC/Repeater Interface. When the signal on

this pin is logic:

• Low, this pin configures the MAC/Repeater Interface as a Media

Independent Interface.

• High, this pin configures the MAC/Repeater Interface as a Stream

Interface.

NOD/REP

Input

Node/Repeater (Select).

This selection on this pin affects both the SQE test and the Carrier

Sense (CSR) signal. When the signal on this pin is logic:

• Low, this pin enables the ICS1893 to default to node operations.

• High, this pin enables the ICS1893 to default to repeater

operations.

REF_IN

Input

(Frequency) Reference Input.

This pin is connected to a 25-MHz oscillator. For a tolerance, see

Section 10.5.1, “Timing for Clock Reference In (REF_IN) Pin”.

REF_OUT

Input

(Frequency) Reference Output.

This pin is eserved and must be left unconnected.

RESETn

Input

(System) Reset (Active Low).

• When the signal on this active-low pin is logic:

– Low, the ICS1893 is in hardware reset.

– High, the ICS1893 is operational.

• For more information on hardware resets, see the following:

– Section 5.1.2.1, “Hardware Reset”

– Section 10.5.18, “Reset: Hardware Reset and Power-Down”

Table 9-4.

Configuration Pins (Continued)

Name

Number

Type

Pin Description

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