ICS1574B

8

]

1

[

P]

0

[

PN

I

A

G

)

n

a

i

d

a

r

/

A

µ

(

00

5

0

.

0

01

5

1

.

0

10

5

.

0

11

5

.

1

]

2

[

V]

1

[

V]

0

[

V

N

I

A

G

O

C

V

)

t

l

o

V

/

z

H

M

(

10

0

0

3

10

1

5

4

11

0

0

6

111

0

8

BIT(S)

BIT REF.

DESCRIPTION

15

Reserved

Must be set to 0.

16

AUX_PCLK

Must be set to 0 except when in the AUX-EN test mode.

When in the AUX-EN test mode, this bit controls the

PCLK output.

17 – 24

Reserved

Must be set to 0.

25 – 27

V[0]..V[2]

Sets the gain of VCO

28

Reserved

Must be set to 1.

29 – 30

P[0]..P[1]

Sets the gain of the phase detector according to this table:

31

Reserved

Must be set to 0.

32

P[2]

Phase detector tuning bit. Should normally be set to one.

See text.

33 – 38

M[0]..M[5]

M counter control bits. Modulus = value + 1.

39

PCLKEN_POL

When = 0, PCLK output enabled when PCLKEN input is

low. When = 1, PCLK output enabled when PCLKEN input

is high.

40

DBLFREQ

Doubles modulus of dual-modulus prescaler (from 6 / 7 to

12 /14).

41 – 44

A[0]..A[3]

Controls A counter. When set to zero, modulus = 7.

Otherwise, modulus = 7 for "value" underflows of the

prescaler, and modulus = 6 thereafter until M counter

underflows.