54 DEBUG PROCEDURE

Evaluation of the DP83231 should begin by tying the CRD

pins are above 2V This will disable the differential phase

comparator allowing the crystal resonator to run at its center

frequency and will keep the part out of a test mode The first

PLL (see

Figure 5-2 ) should be evaluated The variable ca-

pacitor in the crystal resonator circuitry should be tuned so

that the crystal resonator oscillates at 1041666 MHz If the

oscillator circuit fails to oscillate the voltage levels of the

OSC IN and OSC OUT pins should be examined The DC

voltage on these pins should be equal to approximately

tors which form the oscillator tank circuit should be returned

to the isolated ground branch in close proximity After

and verify that this frequency is twelve times the crystal fre-

quency If this is not true then the VCO FLTR output should

be examined for possible PC board shorts opens or filter

instability The VCO FLTR pin should be stable at approxi-

mately a 15V DC level in operation

If the VCO FLTR pin is oscillating then the loop filter compo-

nents for this pin were either chosen inappropriately or were

placed in the incorrect position

Once it is known that the first PLL is working force CRD EN

Figure 5-3 ) To see

how well the second loop is working examine the DIF AMP

pin If the incoming data rate is exactly 625 MHz and the

crystal resonator was accurately adjusted as described

above then the DIF AMP pin voltage should be stable at

approximately 225V

The voltage at this pin will vary

from the nominal value dependent on temperature and data

rate frequency error If this pin is oscillating then the OSC

FLTR pins are unstable and the filters should be examined

for possible PC board shorts opens or instability If the DIF

AMP pin is near ground then check to see if the ELB input is

selecting the correct data input If the DIF AMP pin contin-

KHz (50 PPM) FDDI system data rate specification

TLF10384 – 22

FIGURE 5-2 1st PLL

TLF10384 – 23

FIGURE 5-3 2nd PLL

14