ICS680-01

NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER

ZDB AND SYNTHESIZER

IDT™ / ICS™ NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER 3

ICS680-01

REV H 051310

External Components

The ICS680-01 requires a minimum number of external

components for proper operation.

Decoupling Capacitor

A decoupling capacitor of 0.01µF must be connected

between VDD (pins 5 and 16) and GND (pins 6 and 15), as

close to these pins as possible. For optimum device

performance, the decoupling capacitor should be mounted

on the component side of the PCB. Avoid the use of vias in

the decoupling circuit.

Series Termination Resistor

When the PCB trace between the clock outputs and the

loads are over 1 inch, series termination should be used. To

series terminate a 50

Ω trace (a commonly used trace

impedance) place a 33

Ωresistor in series with the clock line,

as close to the clock output pin as possible. The nominal

impedance of the clock output is 20

Ω.

Crystal Information

The crystal used should be a fundamental mode (do not use

third overtone), parallel resonant. Crystal capacitors should

be connected from pins X1 to ground and X2 to ground to

optimize the initial accuracy. The value of these capacitors

is given by the following equation crystal caps (pF) =

(CL-6)x2

In the equation, CL is the crystal load capacitance. So for a

crystal with a 16 pF load capacitance, two 20 pF[(16-6)x2]

capacitors should be used

PCB Layout Recommendations

For optimum device performance and lowest output phase

noise, the following guidelines should be observed.

1) The 0.01µF decoupling capacitor should be mounted on

the component side of the board as close to the VDD pin as

possible. No vias should be used between decoupling

capacitor and VDD pin. The PCB trace to VDD pin should

be kept as short as possible, as should the PCB trace to the

ground via.

2) The external crystal should be mounted just next to the

device with short traces. The X1 and X2 traces should not

be routed next to each other with minimum spaces, instead

they should be separated and away from other traces.

3) To minimize EMI, the 33

Ω series termination resistor (if

needed) should be placed close to the clock output.

4) An optimum layout is one with all components on the

same side of the board, minimizing vias through other signal

layers. Other signal traces should be routed away from the

ICS680-01. This includes signal traces just underneath the

device, or on layers adjacent to the ground plane layer used

by the device.

18

VDD

Power

Connect to voltage supply.

19

ICLK

Input

Zero Delay Buffer Input. Weak Internal pull-up.

20

25M

Output

25 MHz reference output clock. Weak internal pull-down when tri-state.

21

S1

Input

Select pin 1. See table above.

22

PDTS

Power

Power-down tri-state. Powers down entire chip and tri-states outputs

when low. Internal pull-up resistor.

23

VDD

Power

Connect to voltage supply.

24

X2

XO

Crystal output. Connect this pin to a crystal. Float for clock input.

Pin

Number

Pin

Name

Pin

Type

Pin Description