ICS650-36

NETWORKING AND PCI CLOCK SOURCE

CLOCK SYNTHESIZER

IDT™ / ICS™ NETWORKING AND PCI CLOCK SOURCE

3

ICS650-36

REV F 051310

External Components

Decoupling Capacitor

As with any high performance mixed-signal IC, the

ICS650-36 must be isolated from system power supply

noise to perform optimally.

A decoupling capacitor of 0.01µF must be connected

between each VDD and the PCB ground plane.

Series Termination Resistor

Clock output traces over one inch should use series

termination. To series terminate a 50

Ω trace (a commonly

used trace impedance), place a 33

Ω resistor in series with

the clock line, as close to the clock output pin as possible.

The nominal impedance of the clock output is 20

Ω.

Crystal Load Capacitors

The device crystal connections should include pads for

small capacitors from X1 to ground and from X2 to ground.

These capacitors are used to adjust the stray capacitance of

the board to match the nominally required crystal load

capacitance. Because load capacitance can only be

increased in this trimming process, it is important to keep

stray capacitance to a minimum by using very short PCB

traces (and no vias) between the crystal and device. Crystal

capacitors must be connected from each of the pins X1 and

X2 to ground.

The value (in pF) of these crystal caps should equal (CL -6

pF)*2. In this equation, CL= crystal load capacitance in pF.

Example: For a crystal with a 16 pF load capacitance, each

crystal capacitor would be 20 pF [(16-6) x 2 = 20].

PCB Layout Recommendations

Observed the following guidelines for optimum device

performance and lowest output phase noise:

1) The 0.01µF decoupling capacitors should be mounted on

the component side of the board as close to the VDD pin as

possible. No vias should be used between the decoupling

capacitors and VDD pins. The PCB trace to VDD pins

should be kept as short as possible, as should the PCB

trace to the ground via.

2) The external crystal should be mounted just next to the

device with short traces. The X1 and X2 traces should not

be routed next to each other with minimum spaces, instead

they should be separated and away from other traces.

3) Place the 33

Ω series termination resistor (if needed)

close to the clock output to minimize EMI.

4) An optimum layout is one with all components on the

same side of the board, minimizing vias through other signal

layers. Other signal traces should be routed away from the

ICS650-36. This includes signal traces just underneath the

device, or on layers adjacent to the ground plane layer used

by the device.

14

REF

Output

Reference 25 MHz clock output. Weak internal pull-down when

tri-state.

15

GND

Power

Connect to ground.

16

VDD

Power

Connect to +3.3 V.

Pin

Number

Pin

Name

Pin

Type

Pin Description