DATASHEET

LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT

ICS554-01A

IDT™ / ICS™ LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT

1

ICS554-01A

REV D 051310

Description

The ICS554-01A is a low skew clock buffer with a single

complimentary PECL input to four PECL outputs. Part of

IDT’s Clock BlocksTM family, this is our lowest skew PECL

clock buffer. The ICS554-01A is footprint compatible with

the ICS554-01, but requires fewer passive components for

termination thus providing a cost-saving alternative. For

parts which do not require PECL inputs or outputs, see the

ICS553 for a 1 to 4 low skew buffer, or the ICS552-02 for a

1 to 8 low skew buffer. For more than 8 outputs see the

MK74CBxxx BuffaloTM series of clock drivers.

IDT makes many non-PLL and PLL based low skew output

devices as well as Zero Delay Buffers to synchronize

clocks. Contact us for all of your clocking needs.

Features

• Input frequency up to 200 MHz

• Advanced CMOS process

• Outputs are skew matched to within 50 ps

• Packaged in 16-pin TSSOP, Pb-free

• One PECL input to 4 PECL output clock drivers

• Operating Voltages of 3.3 V or 5 V

• Industrial temperature range

• Functional equivalent to ICS554-01

• Simplified passive termination network compared to

ICS554-01

Block Diagram

IN

IN

Q0

Q0

Q1

Q1

Q2

Q2

Q3

Q3

VDD

VSS