ICS348-22

QUAD PLL CLOCK SYNTHESIZER

EPROM CLOCK SYNTHESIZER

IDT™ / ICS™ QUAD PLL CLOCK SYNTHESIZER

4

ICS348-22

REV B 012005

External Components

Series Termination Resistor

Clock output traces should use series termination. To

series terminate a 50

Ω trace (a commonly used trace

impedance), place a 33

Ω resistor in series with the

clock line, as close to the clock output pin as possible.

The nominal impedance of the clock output is 20

Ω.

Decoupling Capacitors

Decoupling capacitors of 0.01µF must be connected

between each VDD and the PCB ground plane.

Crystal Load Capacitors

The device crystal connections should include pads for

small capacitors from X1 to ground and from X2 to

ground. These capacitors are used to adjust the stray

capacitance of the board to match the nominally

required crystal load capacitance. Because load

capacitance can only be increased in this trimming

process, it is important to keep stray capacitance to a

minimum by using very short PCB traces (and no vias)

been the crystal and device. Crystal capacitors must be

connected from each of the pins X1 and X2 to ground.

The value (in pF) of these crystal caps should equal (CL

-6 pF)*2. In this equation, CL= crystal load capacitance

in pF. Example: For a crystal with a 16 pF load

capacitance, each crystal capacitor would be 20 pF

[(16-6) x 2] = 20.

PCB Layout Recommendations

For optimum device performance and lowest output

phase noise, the following guidelines should be

observed.

1) Each 0.01µF decoupling capacitor should be

mounted on the component side of the board as close

to the VDD pin as possible. No vias should be used

between decoupling capacitor and VDD pin. The PCB

trace to VDD pin should be kept as short as possible, as

should the PCB trace to the ground via.

2) The external crystal should be mounted just next to

the device with short traces. The X1 and X2 traces

should not be routed next to each other with minimum

spaces, instead they should be separated and away

from other traces.

3) To minimize EMI, the 33

Ωseries termination resistor,

if needed, should be placed close to the clock output.

4) An optimum layout is one with all components on the

same side of the board, minimizing vias through other

signal layers

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