ICS307-03

SERIALLY PROGRAMMABLE CLOCK SOURCE

SER PROG CLOCK SYNTHESIZER

IDT® SERIALLY PROGRAMMABLE CLOCK SOURCE

9

ICS307-03

REV L 032911

Setting the PLL Loop Response

The PLL loop response is determined both by fixed device

characteristics and by other characterizes set by the user.

This includes the values of RS and CS as shown in the PLL

Components figure on this page.

The PLL loop bandwidth is approximated by:

Where:

RS = Value of resistor RS in loop filter in Ohms

ICP = Charge pump current in amps

KO = VCO Gain in Hz/V

FV Divider = 12 to 2055

The above equation calculates the “normalized” loop

bandwidth (denoted as “NBW”) which is approximately

equal to the - 3dB bandwidth. NBW does not take into

account the effects of damping factor or the second pole

imposed by CP. It does, however, provide a useful

approximation of filter performance.

To prevent jitter due to modulation of the PLL by the phase

detector frequency, the following general rule should be

observed:

.

The PLL loop damping factor is determined by:

Where:

CS = Value of capacitor CS in loop filter in Farads

= 300e-12 in Farads

Default Register Values

At power-up, the registers are set to:

ref divide = 5

VCO divide = 50

output divide = 10 (CLK1)

output divide = 2 (CLK2)

output divide = 2 (CLK3)

bit 123, 124 = 1

ICP = 3.75 µA

R = 16k

Default programming word is:

0x31FFDFFEE3BFFFFFFFFFFFFFFFF055FF2

NBW(PLL)

R

S

I

CP

×

K

O

×

2

π FV Divider

×

------------------------------------------

=

NBW(VCO PLL)

f(Phase Detector)

10

---------------------------------------

≤

DF(VCLK)

R

S

2

------

I

CP

C

S

×

K

O

×

FV Divider

------------------------------------

×

=