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AD7650 датащи(PDF) 27 Page - Analog Devices |
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AD7650 датащи(HTML) 27 Page - Analog Devices |
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27 / 32 page ![]() AD7610 Rev. 0 | Page 27 of 32 External Clock Data Read After/During Conversion It is also possible to begin to read data after conversion and continue to read the last bits after a new conversion has been initiated. This method allows the full throughput and the use of a slower SDCLK frequency. Again, it is recommended to use a discontinuous SDCLK whenever possible to minimize potential incorrect bit decisions. For the different modes, the use of a slower SDCLK such as 20 MHz in warp mode, 15 MHz in normal mode and 13 MHz in impulse mode can be used. SDIN SDOUT D0 1 2 3 15 16 BUSY EXT/INT = 1 INVSCLK = 0 CS SDCLK 4 D2 D1 17 18 SER/PAR = 1 RD = 0 14 D15 D14 D13 X15 X14 19 X0 X2 X1 X15 X14 X13 Y15 Y14 t31 t31 X* t32 t16 t33 t34 t37 t35 t36 *A DISCONTINUOUS SDCLK IS RECOMMENDED. Figure 42. Slave Serial Data Timing for Reading (Read After Convert) SDOUT D0 12 3 BUSY EXT/INT = 1 INVSCLK = 0 CS SDCLK 15 D1 SER/PAR = 1 RD = 0 16 D15 D14 DATA = SDIN t31 t31 t32 t16 t37 t35 t36 CNVST X* X* X* X* X* X* t27 *A DISCONTINUOUS SDCLK IS RECOMMENDED. Figure 43. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) |
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