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AM79C874VC датащи(PDF) 12 Page - Advanced Micro Devices |
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AM79C874VC датащи(HTML) 12 Page - Advanced Micro Devices |
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12 / 60 page ![]() 12 Am79C874 P R E L I M INARY REFCLK Clock Input Input, Pull-Down This pin connects to a 25-MHz +50 ppm clock source with a 40% to 60% duty cycle. When a crystal input is used, this pin should be pulled low via a 1 k W resistor. XTL± Crystal Inputs Analog Input These pins should be connected to a 25-MHz crystal. The crystal should be parallel resonant and have a fre- quency stability of +100 ppm and a frequency tolerance of +50 ppm. REFCLK (Pin 5) should be pulled low when the crystal is used as a clock source. These pins may be left unconnected when REFCLK is used as a clock source. CLK25 25 MHz Clock Output When the CLK25EN pin is pulled low, the CLK25 pin provides a continuous 25 MHz clock to the MAC. BURN_IN Test Enable Input, Pull-Down When pulled high via a 10 k W resistor, this pin forces the NetPHY-1LP device into Burn-in mode for reliability assurance control. When left unconnected the device operates normally. TEST2 Test Output Analog Output When BURN_IN (pin 7) is pulled high, this pin serves as a test mode output monitor pin. TEST2 can be left unconnected when the device is operating. RST Reset Input, Pull-Up A LOW input forces the NetPHY-1LP device to a known reset state. The chip can also be reset through internal power-on-reset or MII Register 0, bit 15. PWRDN Power Down Input, Pull-Down If this pin is pulled high via a 10 k W resistor on the rising edge of reset, the device will power down the analog modules and reset the digital circuits. However, the de- vice will still respond to MDC/MDIO data. The same power-down state can also be achieved through the MII Register 0, bit 11. However, the device will respond ac- tivity on the PWRDN pin even when bit 11 is not set. When left unconnected, the device operates normally. PHYAD[4:0] PHY Address Input/Output, Pull-Up These pins allow 32 configurable PHY addresses. The PHYAD will also determine the scramble seed, which helps to reduce EMI when there are multiple ports switching at the same time (repeater/switch applica- tions). Each pin should either be pulled low via a 1 k W - 4.7 kW resistor (set bit to zero) or left unconnected (set bit to 1) in order to achieve the desired PHY ad- dress. New address changes take effect after a reset has been issued, or at power up. In PCS bypass mode, PHYAD[4:0] and GPIO[1:0] serves as 10BASE-T serial input and output. Note: In GPSI mode, the PHYAD pins must be set to addresses other than 00h. GPIO[0]/10TXD--/7Wire General Purpose I/O 0 Input/Output, Pull-Up If this pin is pulled low via a 10 k W resistor, on the rising edge of reset, the device will operate in 10BASE-T 7-wire (GPSI) mode. If this pin is left unconnected dur- ing the rising edge of reset, the device will operate in standard MII mode. After the reset operation has completed, this pin can function as an input or an output (dependent on the value of GPIO[0] DIR (MII Register 16, bit 6). If MII Register 16, bit 6 is set HIGH, GPIO[0] is an input. The input value on the GPIO[0] pin will be reflected in MII Register 16, bit 7 – GPIO[0] Data. If MII Register 16, bit 6 is set LOW, GPIO[0] is an output. The value of MII Register 16, bit 7 will be reflected on the GPIO[0] output pin. GPIO[1]/TP125 General Purpose I/O 1 Input/Output, Pull-Down If this pin is pulled high via a 10 k W resistor, on the ris- ing edge of reset, the device will be enabled for use with a 1.25:1 transmit ratio transformer. If this pin is left unconnected during the rising edge of reset, the device will be enabled for use with a 1:1 transmit ratio transformer. After the reset operation has completed, this pin can function as an input or an output (dependent on the value of GPIO[1] DIR – MII Register 16, bit 8). If MII Register 16, bit 8 is set HIGH, GPIO[1] is an input. The input value on the GPIO[1] pin will be reflected in MII Register 16, bit 9 – GPIO[1] Data. If MII Register 16, bit 8 is set LOW, GPIO[1] is an output. The value of MII Register 16, bit 9 will be reflected on the GPIO[1] output pin. MDIO Management Data Input/Output Pull-Down This pin is a bidirectional data interface used by the MAC to access management registers within the Net- PHY-1LP device. This pin has an internal pull-down, therefore, it requires a 1.5 k W pull-up resistor as speci- fied in IEEE 802.3 when interfaced with a MAC. This pin can be left unconnected when management is not used. |
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