CYT3DLABFS datasheet(21/207 Pages) INFINEON

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Datasheet

21 of 207

002-27763 Rev.*H

2023-03-03

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 single

Functional description

3.3.14

Trigger multiplexer

CYT3DL supports connecting various peripherals using trigger signals. Triggers are used to inform a peripheral of

the occurrence of an event or change of state. These triggers are used to affect or initiate some action in other

peripherals. The trigger multiplexer is used to route triggers from a source peripheral to a destination. Triggers

provide active logic functionality and are typically supported in Active mode.

3.4

Graphics

CYT3DL supports one instance of the graphics subsystem which includes 2048 KB of embedded Video RAM, a 2D

graphics core and interfaces for video input and output processing.

CYT3DL supports 4-lane MIPI CSI-2 interface for up to HD (1920 × 720) resolution video inputs and single channel

FPD-link interface for up to HD (1920 × 720) resolution video output. The 2D graphics core supports a BLock Image

Transfer (BLIT) engine for faster graphics rendering to memory or on-the-fly to display, a drawing engine for

acceleration of vector graphics rendering and a command sequencer for setup and control of the rendering

process. The video I/O supports a composition engine for scene composition from display layers, a display engine

for video timing generation, and display functions and a capture engine for video input processing. The device

also supports perspective correction for 3D effects ("2.5D"). One layer, such as head-up displays, can be warped

on-the-fly.

3.5

I/Os

CYT3DL has up to 135 programmable I/Os.

The I/Os are organized as logical entities called ports, which are a maximum of 8 bits wide. During power-on and

reset, the I/Os are forced to the High-Z state. During the Hibernate mode, the I/Os are frozen.

Every I/O can generate an interrupt (if enabled) and each port has an interrupt request (IRQ) and interrupt service

routine (ISR) associated with it.

I/O port power source mapping is listed in Table 3-4. The associated supply determines the VOH, VOL, VIH, and VIL

levels when configured for CMOS and Automotive thresholds.

All I/Os support the following programmable drive modes:

• High impedance

•Resistive pull-up

•Resistive pull-down

• Open drain with strong pull-down

• Open drain with strong pull-up

• Strong pull-up or pull-down

• Weak pull-up or pull-down

CYT3DL has four types of programmable GPIOs: GPIO Standard, GPIO Enhanced, GPIO SMC, and HSIO Standard

with Low noise. Only GPIO_STD, GPIO_ENH, and GPIO_SMC have the capability to wakeup the device from

DeepSleep mode. All these I/Os have GPIO input/output functionality, some of these might need special

configuration[16].

Table 3-4

I/O port power source

Supply pins

Ports

VDDD[15]

VDDIO_GPIO_1[15]

P1, P2, P3

VDDIO_GPIO_2[15]

P4, P5, P6

VDDIO_SMC[15]

P7, P8, P9

VDDIO_HSIO

P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21

Notes

15.Ensure that VDDD ≥ (VDDIO_GPIO_1 - 0.3 V) ≥ (VDDIO_GPIO_2 - 0.3 V).

16.Refer to the family-specific Architecture TRM for more information on the I/O configurations (002-25800, TRAVEO™ T2G Automotive

MCU cluster 2D architecture technical reference manual).

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