INDUSTRIALTEMPERATURERANGE

74FCT543AT/CT

FASTCMOSOCTALLATCHEDTRANSCEIVER

1

Feb.11.20

INDUSTRIAL TEMPERATURE RANGE

FEATURES:

• A and C grades

• Low input and output leakage

≤≤≤≤≤1µA (max.)

• CMOS power levels

• True TTL input and output compatibility:

–VOH = 3.3V (typ.)

–VOL = 0.3V (typ.)

• High Drive outputs (-15mA IOH, 64mA IOL)

• Meets or exceeds JEDEC standard 18 specifications

• Power off disable outputs permit "live insertion"

• Available in SOIC and QSOP packages

FUNCTIONAL BLOCK DIAGRAM

74FCT543AT/CT

FAST CMOS

OCTAL LATCHED

TRANSCEIVER

DESCRIPTION:

TheFCT543Tisanon-invertingoctaltransceiverbuiltusinganadvanced

dual metal CMOS technology. This device contains two sets of eight D-type

latches with separate input and output controls for each set. For data flow

fromAtoB,forexample,theA-to-BEnable(CEAB)inputmustbelowinorder

to enter data from A0–A7 or to take data from B0–B7, as indicated in the

Function Table. With CEAB low, a low signal on the A-to-B Latch Enable

(LEAB) input makes the A-to-B latches transparent; a subsequent low-to-

high transition of the LEAB signal puts the A latches in the storage mode and

theiroutputsnolongerchangewiththeAinputs. WithCEABandOEAB both

low, the 3-state B output buffers are active and reflect the data present at the

output of the A latches. Control of data from B to A is similar, but uses the

CEBA, LEBA and OEBA inputs.

A1

Q

OEBA

A2

A3

A4

A5

A6

A7

B1

B2

B3

B4

B5

B6

B7

CEBA

LEBA

OEAB

CEAB

LEAB

DETAIL A x 7

D

LE

Q

D

LE

DETAIL A

A0

B0