6

INDUSTRIALTEMPERATURERANGE

IDT5T9890

EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER

JTAG/ I2C SERIAL DESCRIPTION

Bit

Description

95:62 Reserved Bits. Set bits 95:62 to '0'.

61

Input interface selection for control pins (REF_SEL, PD, PLL_EN, OMODE, nSOE). When bit 61 is ‘1’, the control pins are 2.5V LVTTL. When bit 61 is ‘0’,

the control pins are 1.8V LVTTL.

60

VCO frequency range. When ‘0’, range is 50MHz-125MHz. When ‘1’, range is 100MHz-250MHz.

59

Output’s disable state. See corresponding external pin OMODE for Pin Description table.

58

Positive/Negative edge control. When ‘0’/’1’, the outputs are synchronized with the negative/positive edge of the reference clock.

57

PLL enable/disable. See corresponding external pin PLL_EN in Pin Description table.(1)

56

Output disable/enable for 1Q[1:0] outputs. See corresponding external pin 1SOE in Pin Description table.

55

Output disable/enable for 2Q[1:0] outputs. See corresponding external pin 2SOE in Pin Description table.

54

Output disable/enable for 3Q[1:0] outputs. See corresponding external pin 3SOE in Pin Description table.

53

Output disable/enable for 4Q[1:0] outputs. See corresponding external pin 4SOE in Pin Description table.

52

Output disable/enable for 5Q[1:0] outputs. See corresponding external pin 5SOE in Pin Description table.

51

FB Divide-by-N selection

50

FB Divide-by-N selection

49

FB Divide-by-N selection

48

FB Divide-by-N selection

47

Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 1

46

Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 1

45

Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 2

44

Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 2

43

Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 3

42

Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 3

41

Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 4

40

Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 4

39

Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 5

38

Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 5

37

FB output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on FB bank

36

FB output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on FB bank

35

REF0 Input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential

34

REF0 Input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential

33

REF1 input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential

32

REF1 input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential

31

FB input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential

30

FB input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential

29

Skew or frequency selection for bank 1

28

Skew or frequency selection for bank 1

27

Skew or frequency selection for bank 1

26

Skew or frequency selection for bank 1

25

Skew or frequency selection for bank 1

24

Skew or frequency selection for bank 2

23

Skew or frequency selection for bank 2

22

Skew or frequency selection for bank 2

NOTE:

1. Only for EEPROM operation; bit 57 must be set to 0 to enable the PLL for proper EEPROM operation. The EEPROM access times are based on the VCO frequency of the PLL

(refer to the EEPROM Operation section).