AD9397SLASHPCB datasheet(11/28 Pages) AD

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AD9397

Rev. 0 | Page 11 of 28

TIMING

The output data clock signal is created so that its rising edge

always occurs between data transitions and can be used to latch

the output data externally.

Figure 3 shows the timing operation of the AD9397.

tPER

tDCYCLE

tSKEW

DATACK

DATA

HSOUT

Figure 3. Output Timing

HSYNC TIMING

Horizontal sync (HSYNC) is processed in the AD9397 to

eliminate ambiguity in the timing of the leading edge with

respect to the phase-delayed pixel clock and data.

The HSYNC input is used as a reference to generate the pixel

sampling clock. The sampling phase can be adjusted, with

respect to HSYNC, through a full 360° in 32 steps via the phase

adjust register (to optimize the pixel sampling time). Display

systems use HSYNC to align memory and display write cycles,

so it is important to have a stable timing relationship between

the HSYNC output (HSOUT) and data clock (DATACK).

VSYNC FILTER AND ODD/EVEN FIELDS

The VSYNC filter is used to eliminate spurious VSYNCs,

maintain a consistent timing relationship between the VSYNC

and HSYNC output signals, and generate the odd/even field

output.

The filter works by examining the placement of VSYNC

with respect to HSYNC and, if necessary, slightly shifting

it in time at the VSOUT output. The goal is to keep the

VSYNC and HSYNC leading edges from switching at the

same time, eliminating confusion as to when the first line

of a frame occurs. Enabling the VSYNC filter is done with

all cases, including interlaced video, and is required when using

the HSYNC per VSYNC counter. Figure 4 and Figure 5

illustrate even/odd field determination in two situations.

FIELD 1

FIELD 0

SYNC SEPARATOR THRESHOLD

FIELD 1

FIELD 0

HSIN

VSIN

VSOUT

O/E FIELD

EVEN FIELD

QUADRANT

Figure 4. VSYNC Filter

FIELD 1

FIELD 0

SYNC SEPARATOR THRESHOLD

FIELD 1

FIELD 0

HSIN

VSIN

VSOUT

O/E FIELD

ODD FIELD

QUADRANT

Figure 5. VSYNC Filter—Odd/Even

DVI RECEIVER

The DVI receiver section of the AD9397 allows the reception of

a digital video stream compatible with DVI 1.0. Embedded in

this data stream are HSYNCs, VSYNCs, and display enable

(DE) signals. DVI restricts the received format to RGB, but the

inclusion of a programmable color space converter (CSC)

allows the output to be tailored to any format necessary. With

this, the scaler following the AD9397 can specify that it always

wishes to receive a particular format—for instance, 4:2:2

YCrCb—regardless of the transmitted mode. If RGB is sent, the

CSC can easily convert that to 4:2:2 YCrCb while relieving the

scaler of this task.

DE GENERATOR

The AD9397 has an onboard generator for DE, for start of

active video (SAV), and for end of active video (EAV), all of

which are necessary for describing the complete data stream for

a BT656-compatible output. In addition to this particular

output, it is possible to generate the DE for cases in which a

scaler is not used. This signal alerts the following circuitry as to

which are displayable video pixels.

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